GF018hv5v_mcu_sc7_2016q3v1/verilog/GF018hv5v_mcu_sc7_udp.v

//****************************************************************************//
//                                                                            //
/* Revision: 0.4                                                              */
// File generated on Wed Apr 13 17:18:58 PDT 2016. ( GF   )                   //
//****************************************************************************//


`timescale 1ns/1ps

// udp_data_begin


`celldefine
module ADDF_X1_7T5P0_func( S, A, CI, B, CO, VDD, VSS );
input A, B, CI;
inout VDD, VSS;
output CO, S;

	wire CO_row1;

	and MGM_BG_0( CO_row1, A, B );

	wire CO_row2;

	and MGM_BG_1( CO_row2, A, CI );

	wire CO_row3;

	and MGM_BG_2( CO_row3, B, CI );

	or MGM_BG_3( CO, CO_row1, CO_row2, CO_row3 );

	wire S_row1;

	and MGM_BG_4( S_row1, A, B, CI );

	wire B_inv_for_ADDF_X1_7T5P0;

	not MGM_BG_5( B_inv_for_ADDF_X1_7T5P0, B );

	wire CI_inv_for_ADDF_X1_7T5P0;

	not MGM_BG_6( CI_inv_for_ADDF_X1_7T5P0, CI );

	wire S_row2;

	and MGM_BG_7( S_row2, B_inv_for_ADDF_X1_7T5P0, CI_inv_for_ADDF_X1_7T5P0, A );

	wire A_inv_for_ADDF_X1_7T5P0;

	not MGM_BG_8( A_inv_for_ADDF_X1_7T5P0, A );

	wire S_row3;

	and MGM_BG_9( S_row3, A_inv_for_ADDF_X1_7T5P0, CI_inv_for_ADDF_X1_7T5P0, B );

	wire S_row4;

	and MGM_BG_10( S_row4, A_inv_for_ADDF_X1_7T5P0, B_inv_for_ADDF_X1_7T5P0, CI );

	or MGM_BG_11( S, S_row1, S_row2, S_row3, S_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ADDF_X2_7T5P0_func( S, A, CI, B, CO, VDD, VSS );
input A, B, CI;
inout VDD, VSS;
output CO, S;

	wire CO_row1;

	and MGM_BG_0( CO_row1, A, B );

	wire CO_row2;

	and MGM_BG_1( CO_row2, A, CI );

	wire CO_row3;

	and MGM_BG_2( CO_row3, B, CI );

	or MGM_BG_3( CO, CO_row1, CO_row2, CO_row3 );

	wire S_row1;

	and MGM_BG_4( S_row1, A, B, CI );

	wire B_inv_for_ADDF_X2_7T5P0;

	not MGM_BG_5( B_inv_for_ADDF_X2_7T5P0, B );

	wire CI_inv_for_ADDF_X2_7T5P0;

	not MGM_BG_6( CI_inv_for_ADDF_X2_7T5P0, CI );

	wire S_row2;

	and MGM_BG_7( S_row2, B_inv_for_ADDF_X2_7T5P0, CI_inv_for_ADDF_X2_7T5P0, A );

	wire A_inv_for_ADDF_X2_7T5P0;

	not MGM_BG_8( A_inv_for_ADDF_X2_7T5P0, A );

	wire S_row3;

	and MGM_BG_9( S_row3, A_inv_for_ADDF_X2_7T5P0, CI_inv_for_ADDF_X2_7T5P0, B );

	wire S_row4;

	and MGM_BG_10( S_row4, A_inv_for_ADDF_X2_7T5P0, B_inv_for_ADDF_X2_7T5P0, CI );

	or MGM_BG_11( S, S_row1, S_row2, S_row3, S_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ADDF_X4_7T5P0_func( S, A, CI, B, CO, VDD, VSS );
input A, B, CI;
inout VDD, VSS;
output CO, S;

	wire CO_row1;

	and MGM_BG_0( CO_row1, A, B );

	wire CO_row2;

	and MGM_BG_1( CO_row2, A, CI );

	wire CO_row3;

	and MGM_BG_2( CO_row3, B, CI );

	or MGM_BG_3( CO, CO_row1, CO_row2, CO_row3 );

	wire S_row1;

	and MGM_BG_4( S_row1, A, B, CI );

	wire B_inv_for_ADDF_X4_7T5P0;

	not MGM_BG_5( B_inv_for_ADDF_X4_7T5P0, B );

	wire CI_inv_for_ADDF_X4_7T5P0;

	not MGM_BG_6( CI_inv_for_ADDF_X4_7T5P0, CI );

	wire S_row2;

	and MGM_BG_7( S_row2, B_inv_for_ADDF_X4_7T5P0, CI_inv_for_ADDF_X4_7T5P0, A );

	wire A_inv_for_ADDF_X4_7T5P0;

	not MGM_BG_8( A_inv_for_ADDF_X4_7T5P0, A );

	wire S_row3;

	and MGM_BG_9( S_row3, A_inv_for_ADDF_X4_7T5P0, CI_inv_for_ADDF_X4_7T5P0, B );

	wire S_row4;

	and MGM_BG_10( S_row4, A_inv_for_ADDF_X4_7T5P0, B_inv_for_ADDF_X4_7T5P0, CI );

	or MGM_BG_11( S, S_row1, S_row2, S_row3, S_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ADDH_X1_7T5P0_func( CO, A, B, S, VDD, VSS );
input A, B;
inout VDD, VSS;
output CO, S;

	and MGM_BG_0( CO, A, B );

	wire B_inv_for_ADDH_X1_7T5P0;

	not MGM_BG_1( B_inv_for_ADDH_X1_7T5P0, B );

	wire S_row1;

	and MGM_BG_2( S_row1, B_inv_for_ADDH_X1_7T5P0, A );

	wire A_inv_for_ADDH_X1_7T5P0;

	not MGM_BG_3( A_inv_for_ADDH_X1_7T5P0, A );

	wire S_row2;

	and MGM_BG_4( S_row2, A_inv_for_ADDH_X1_7T5P0, B );

	or MGM_BG_5( S, S_row1, S_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ADDH_X2_7T5P0_func( CO, A, B, S, VDD, VSS );
input A, B;
inout VDD, VSS;
output CO, S;

	and MGM_BG_0( CO, A, B );

	wire B_inv_for_ADDH_X2_7T5P0;

	not MGM_BG_1( B_inv_for_ADDH_X2_7T5P0, B );

	wire S_row1;

	and MGM_BG_2( S_row1, B_inv_for_ADDH_X2_7T5P0, A );

	wire A_inv_for_ADDH_X2_7T5P0;

	not MGM_BG_3( A_inv_for_ADDH_X2_7T5P0, A );

	wire S_row2;

	and MGM_BG_4( S_row2, A_inv_for_ADDH_X2_7T5P0, B );

	or MGM_BG_5( S, S_row1, S_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ADDH_X4_7T5P0_func( A, B, CO, S, VDD, VSS );
input A, B;
inout VDD, VSS;
output CO, S;

	and MGM_BG_0( CO, A, B );

	wire B_inv_for_ADDH_X4_7T5P0;

	not MGM_BG_1( B_inv_for_ADDH_X4_7T5P0, B );

	wire S_row1;

	and MGM_BG_2( S_row1, B_inv_for_ADDH_X4_7T5P0, A );

	wire A_inv_for_ADDH_X4_7T5P0;

	not MGM_BG_3( A_inv_for_ADDH_X4_7T5P0, A );

	wire S_row2;

	and MGM_BG_4( S_row2, A_inv_for_ADDH_X4_7T5P0, B );

	or MGM_BG_5( S, S_row1, S_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND2_X1_7T5P0_func( A1, A2, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND2_X2_7T5P0_func( A1, A2, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND2_X4_7T5P0_func( A2, A1, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND3_X1_7T5P0_func( A1, A2, A3, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2, A3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND3_X2_7T5P0_func( A1, A2, A3, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2, A3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND3_X4_7T5P0_func( A3, A2, A1, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2, A3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND4_X1_7T5P0_func( A1, A2, A3, A4, Z, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2, A3, A4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND4_X2_7T5P0_func( A1, A2, A3, A4, Z, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2, A3, A4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AND4_X4_7T5P0_func( A4, A3, A1, A2, Z, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output Z;

	and MGM_BG_0( Z, A1, A2, A3, A4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ANTENNA_7T5P0_func( I, VDD, VSS );
input I;
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI211_X1_7T5P0_func( A2, ZN, A1, B, C, VDD, VSS );
input A1, A2, B, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI211_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI211_X1_7T5P0, A1 );

	wire B_inv_for_AOI211_X1_7T5P0;

	not MGM_BG_1( B_inv_for_AOI211_X1_7T5P0, B );

	wire C_inv_for_AOI211_X1_7T5P0;

	not MGM_BG_2( C_inv_for_AOI211_X1_7T5P0, C );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI211_X1_7T5P0, B_inv_for_AOI211_X1_7T5P0, C_inv_for_AOI211_X1_7T5P0 );

	wire A2_inv_for_AOI211_X1_7T5P0;

	not MGM_BG_4( A2_inv_for_AOI211_X1_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A2_inv_for_AOI211_X1_7T5P0, B_inv_for_AOI211_X1_7T5P0, C_inv_for_AOI211_X1_7T5P0 );

	or MGM_BG_6( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI211_X2_7T5P0_func( A2, A1, ZN, B, C, VDD, VSS );
input A1, A2, B, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI211_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI211_X2_7T5P0, A1 );

	wire B_inv_for_AOI211_X2_7T5P0;

	not MGM_BG_1( B_inv_for_AOI211_X2_7T5P0, B );

	wire C_inv_for_AOI211_X2_7T5P0;

	not MGM_BG_2( C_inv_for_AOI211_X2_7T5P0, C );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI211_X2_7T5P0, B_inv_for_AOI211_X2_7T5P0, C_inv_for_AOI211_X2_7T5P0 );

	wire A2_inv_for_AOI211_X2_7T5P0;

	not MGM_BG_4( A2_inv_for_AOI211_X2_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A2_inv_for_AOI211_X2_7T5P0, B_inv_for_AOI211_X2_7T5P0, C_inv_for_AOI211_X2_7T5P0 );

	or MGM_BG_6( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI211_X4_7T5P0_func( ZN, A2, A1, B, C, VDD, VSS );
input A1, A2, B, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI211_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI211_X4_7T5P0, A1 );

	wire B_inv_for_AOI211_X4_7T5P0;

	not MGM_BG_1( B_inv_for_AOI211_X4_7T5P0, B );

	wire C_inv_for_AOI211_X4_7T5P0;

	not MGM_BG_2( C_inv_for_AOI211_X4_7T5P0, C );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI211_X4_7T5P0, B_inv_for_AOI211_X4_7T5P0, C_inv_for_AOI211_X4_7T5P0 );

	wire A2_inv_for_AOI211_X4_7T5P0;

	not MGM_BG_4( A2_inv_for_AOI211_X4_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A2_inv_for_AOI211_X4_7T5P0, B_inv_for_AOI211_X4_7T5P0, C_inv_for_AOI211_X4_7T5P0 );

	or MGM_BG_6( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI21_X1_7T5P0_func( A2, ZN, A1, B, VDD, VSS );
input A1, A2, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI21_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI21_X1_7T5P0, A1 );

	wire B_inv_for_AOI21_X1_7T5P0;

	not MGM_BG_1( B_inv_for_AOI21_X1_7T5P0, B );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_AOI21_X1_7T5P0, B_inv_for_AOI21_X1_7T5P0 );

	wire A2_inv_for_AOI21_X1_7T5P0;

	not MGM_BG_3( A2_inv_for_AOI21_X1_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_4( ZN_row2, A2_inv_for_AOI21_X1_7T5P0, B_inv_for_AOI21_X1_7T5P0 );

	or MGM_BG_5( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI21_X2_7T5P0_func( B, ZN, A2, A1, VDD, VSS );
input A1, A2, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI21_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI21_X2_7T5P0, A1 );

	wire B_inv_for_AOI21_X2_7T5P0;

	not MGM_BG_1( B_inv_for_AOI21_X2_7T5P0, B );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_AOI21_X2_7T5P0, B_inv_for_AOI21_X2_7T5P0 );

	wire A2_inv_for_AOI21_X2_7T5P0;

	not MGM_BG_3( A2_inv_for_AOI21_X2_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_4( ZN_row2, A2_inv_for_AOI21_X2_7T5P0, B_inv_for_AOI21_X2_7T5P0 );

	or MGM_BG_5( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI21_X4_7T5P0_func( A2, A1, ZN, B, VDD, VSS );
input A1, A2, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI21_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI21_X4_7T5P0, A1 );

	wire B_inv_for_AOI21_X4_7T5P0;

	not MGM_BG_1( B_inv_for_AOI21_X4_7T5P0, B );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_AOI21_X4_7T5P0, B_inv_for_AOI21_X4_7T5P0 );

	wire A2_inv_for_AOI21_X4_7T5P0;

	not MGM_BG_3( A2_inv_for_AOI21_X4_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_4( ZN_row2, A2_inv_for_AOI21_X4_7T5P0, B_inv_for_AOI21_X4_7T5P0 );

	or MGM_BG_5( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI221_X1_7T5P0_func( B2, B1, ZN, C, A2, A1, VDD, VSS );
input A1, A2, B1, B2, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI221_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI221_X1_7T5P0, A1 );

	wire B1_inv_for_AOI221_X1_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI221_X1_7T5P0, B1 );

	wire C_inv_for_AOI221_X1_7T5P0;

	not MGM_BG_2( C_inv_for_AOI221_X1_7T5P0, C );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI221_X1_7T5P0, B1_inv_for_AOI221_X1_7T5P0, C_inv_for_AOI221_X1_7T5P0 );

	wire B2_inv_for_AOI221_X1_7T5P0;

	not MGM_BG_4( B2_inv_for_AOI221_X1_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A1_inv_for_AOI221_X1_7T5P0, B2_inv_for_AOI221_X1_7T5P0, C_inv_for_AOI221_X1_7T5P0 );

	wire A2_inv_for_AOI221_X1_7T5P0;

	not MGM_BG_6( A2_inv_for_AOI221_X1_7T5P0, A2 );

	wire ZN_row3;

	and MGM_BG_7( ZN_row3, A2_inv_for_AOI221_X1_7T5P0, B1_inv_for_AOI221_X1_7T5P0, C_inv_for_AOI221_X1_7T5P0 );

	wire ZN_row4;

	and MGM_BG_8( ZN_row4, A2_inv_for_AOI221_X1_7T5P0, B2_inv_for_AOI221_X1_7T5P0, C_inv_for_AOI221_X1_7T5P0 );

	or MGM_BG_9( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI221_X2_7T5P0_func( ZN, B2, C, B1, A1, A2, VDD, VSS );
input A1, A2, B1, B2, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI221_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI221_X2_7T5P0, A1 );

	wire B1_inv_for_AOI221_X2_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI221_X2_7T5P0, B1 );

	wire C_inv_for_AOI221_X2_7T5P0;

	not MGM_BG_2( C_inv_for_AOI221_X2_7T5P0, C );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI221_X2_7T5P0, B1_inv_for_AOI221_X2_7T5P0, C_inv_for_AOI221_X2_7T5P0 );

	wire B2_inv_for_AOI221_X2_7T5P0;

	not MGM_BG_4( B2_inv_for_AOI221_X2_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A1_inv_for_AOI221_X2_7T5P0, B2_inv_for_AOI221_X2_7T5P0, C_inv_for_AOI221_X2_7T5P0 );

	wire A2_inv_for_AOI221_X2_7T5P0;

	not MGM_BG_6( A2_inv_for_AOI221_X2_7T5P0, A2 );

	wire ZN_row3;

	and MGM_BG_7( ZN_row3, A2_inv_for_AOI221_X2_7T5P0, B1_inv_for_AOI221_X2_7T5P0, C_inv_for_AOI221_X2_7T5P0 );

	wire ZN_row4;

	and MGM_BG_8( ZN_row4, A2_inv_for_AOI221_X2_7T5P0, B2_inv_for_AOI221_X2_7T5P0, C_inv_for_AOI221_X2_7T5P0 );

	or MGM_BG_9( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI221_X4_7T5P0_func( ZN, B2, B1, C, A1, A2, VDD, VSS );
input A1, A2, B1, B2, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI221_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI221_X4_7T5P0, A1 );

	wire B1_inv_for_AOI221_X4_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI221_X4_7T5P0, B1 );

	wire C_inv_for_AOI221_X4_7T5P0;

	not MGM_BG_2( C_inv_for_AOI221_X4_7T5P0, C );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI221_X4_7T5P0, B1_inv_for_AOI221_X4_7T5P0, C_inv_for_AOI221_X4_7T5P0 );

	wire B2_inv_for_AOI221_X4_7T5P0;

	not MGM_BG_4( B2_inv_for_AOI221_X4_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A1_inv_for_AOI221_X4_7T5P0, B2_inv_for_AOI221_X4_7T5P0, C_inv_for_AOI221_X4_7T5P0 );

	wire A2_inv_for_AOI221_X4_7T5P0;

	not MGM_BG_6( A2_inv_for_AOI221_X4_7T5P0, A2 );

	wire ZN_row3;

	and MGM_BG_7( ZN_row3, A2_inv_for_AOI221_X4_7T5P0, B1_inv_for_AOI221_X4_7T5P0, C_inv_for_AOI221_X4_7T5P0 );

	wire ZN_row4;

	and MGM_BG_8( ZN_row4, A2_inv_for_AOI221_X4_7T5P0, B2_inv_for_AOI221_X4_7T5P0, C_inv_for_AOI221_X4_7T5P0 );

	or MGM_BG_9( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI222_X1_7T5P0_func( C2, C1, B1, ZN, B2, A2, A1, VDD, VSS );
input A1, A2, B1, B2, C1, C2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI222_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI222_X1_7T5P0, A1 );

	wire B1_inv_for_AOI222_X1_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI222_X1_7T5P0, B1 );

	wire C1_inv_for_AOI222_X1_7T5P0;

	not MGM_BG_2( C1_inv_for_AOI222_X1_7T5P0, C1 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI222_X1_7T5P0, B1_inv_for_AOI222_X1_7T5P0, C1_inv_for_AOI222_X1_7T5P0 );

	wire C2_inv_for_AOI222_X1_7T5P0;

	not MGM_BG_4( C2_inv_for_AOI222_X1_7T5P0, C2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A1_inv_for_AOI222_X1_7T5P0, B1_inv_for_AOI222_X1_7T5P0, C2_inv_for_AOI222_X1_7T5P0 );

	wire B2_inv_for_AOI222_X1_7T5P0;

	not MGM_BG_6( B2_inv_for_AOI222_X1_7T5P0, B2 );

	wire ZN_row3;

	and MGM_BG_7( ZN_row3, A1_inv_for_AOI222_X1_7T5P0, B2_inv_for_AOI222_X1_7T5P0, C1_inv_for_AOI222_X1_7T5P0 );

	wire ZN_row4;

	and MGM_BG_8( ZN_row4, A1_inv_for_AOI222_X1_7T5P0, B2_inv_for_AOI222_X1_7T5P0, C2_inv_for_AOI222_X1_7T5P0 );

	wire A2_inv_for_AOI222_X1_7T5P0;

	not MGM_BG_9( A2_inv_for_AOI222_X1_7T5P0, A2 );

	wire ZN_row5;

	and MGM_BG_10( ZN_row5, A2_inv_for_AOI222_X1_7T5P0, B1_inv_for_AOI222_X1_7T5P0, C1_inv_for_AOI222_X1_7T5P0 );

	wire ZN_row6;

	and MGM_BG_11( ZN_row6, A2_inv_for_AOI222_X1_7T5P0, B1_inv_for_AOI222_X1_7T5P0, C2_inv_for_AOI222_X1_7T5P0 );

	wire ZN_row7;

	and MGM_BG_12( ZN_row7, A2_inv_for_AOI222_X1_7T5P0, B2_inv_for_AOI222_X1_7T5P0, C1_inv_for_AOI222_X1_7T5P0 );

	wire ZN_row8;

	and MGM_BG_13( ZN_row8, A2_inv_for_AOI222_X1_7T5P0, B2_inv_for_AOI222_X1_7T5P0, C2_inv_for_AOI222_X1_7T5P0 );

	or MGM_BG_14( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4, ZN_row5, ZN_row6, ZN_row7, ZN_row8 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI222_X2_7T5P0_func( ZN, C2, C1, B2, B1, A1, A2, VDD, VSS );
input A1, A2, B1, B2, C1, C2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI222_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI222_X2_7T5P0, A1 );

	wire B1_inv_for_AOI222_X2_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI222_X2_7T5P0, B1 );

	wire C1_inv_for_AOI222_X2_7T5P0;

	not MGM_BG_2( C1_inv_for_AOI222_X2_7T5P0, C1 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI222_X2_7T5P0, B1_inv_for_AOI222_X2_7T5P0, C1_inv_for_AOI222_X2_7T5P0 );

	wire C2_inv_for_AOI222_X2_7T5P0;

	not MGM_BG_4( C2_inv_for_AOI222_X2_7T5P0, C2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A1_inv_for_AOI222_X2_7T5P0, B1_inv_for_AOI222_X2_7T5P0, C2_inv_for_AOI222_X2_7T5P0 );

	wire B2_inv_for_AOI222_X2_7T5P0;

	not MGM_BG_6( B2_inv_for_AOI222_X2_7T5P0, B2 );

	wire ZN_row3;

	and MGM_BG_7( ZN_row3, A1_inv_for_AOI222_X2_7T5P0, B2_inv_for_AOI222_X2_7T5P0, C1_inv_for_AOI222_X2_7T5P0 );

	wire ZN_row4;

	and MGM_BG_8( ZN_row4, A1_inv_for_AOI222_X2_7T5P0, B2_inv_for_AOI222_X2_7T5P0, C2_inv_for_AOI222_X2_7T5P0 );

	wire A2_inv_for_AOI222_X2_7T5P0;

	not MGM_BG_9( A2_inv_for_AOI222_X2_7T5P0, A2 );

	wire ZN_row5;

	and MGM_BG_10( ZN_row5, A2_inv_for_AOI222_X2_7T5P0, B1_inv_for_AOI222_X2_7T5P0, C1_inv_for_AOI222_X2_7T5P0 );

	wire ZN_row6;

	and MGM_BG_11( ZN_row6, A2_inv_for_AOI222_X2_7T5P0, B1_inv_for_AOI222_X2_7T5P0, C2_inv_for_AOI222_X2_7T5P0 );

	wire ZN_row7;

	and MGM_BG_12( ZN_row7, A2_inv_for_AOI222_X2_7T5P0, B2_inv_for_AOI222_X2_7T5P0, C1_inv_for_AOI222_X2_7T5P0 );

	wire ZN_row8;

	and MGM_BG_13( ZN_row8, A2_inv_for_AOI222_X2_7T5P0, B2_inv_for_AOI222_X2_7T5P0, C2_inv_for_AOI222_X2_7T5P0 );

	or MGM_BG_14( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4, ZN_row5, ZN_row6, ZN_row7, ZN_row8 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI222_X4_7T5P0_func( ZN, C2, C1, B1, B2, A2, A1, VDD, VSS );
input A1, A2, B1, B2, C1, C2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI222_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI222_X4_7T5P0, A1 );

	wire B1_inv_for_AOI222_X4_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI222_X4_7T5P0, B1 );

	wire C1_inv_for_AOI222_X4_7T5P0;

	not MGM_BG_2( C1_inv_for_AOI222_X4_7T5P0, C1 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_AOI222_X4_7T5P0, B1_inv_for_AOI222_X4_7T5P0, C1_inv_for_AOI222_X4_7T5P0 );

	wire C2_inv_for_AOI222_X4_7T5P0;

	not MGM_BG_4( C2_inv_for_AOI222_X4_7T5P0, C2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, A1_inv_for_AOI222_X4_7T5P0, B1_inv_for_AOI222_X4_7T5P0, C2_inv_for_AOI222_X4_7T5P0 );

	wire B2_inv_for_AOI222_X4_7T5P0;

	not MGM_BG_6( B2_inv_for_AOI222_X4_7T5P0, B2 );

	wire ZN_row3;

	and MGM_BG_7( ZN_row3, A1_inv_for_AOI222_X4_7T5P0, B2_inv_for_AOI222_X4_7T5P0, C1_inv_for_AOI222_X4_7T5P0 );

	wire ZN_row4;

	and MGM_BG_8( ZN_row4, A1_inv_for_AOI222_X4_7T5P0, B2_inv_for_AOI222_X4_7T5P0, C2_inv_for_AOI222_X4_7T5P0 );

	wire A2_inv_for_AOI222_X4_7T5P0;

	not MGM_BG_9( A2_inv_for_AOI222_X4_7T5P0, A2 );

	wire ZN_row5;

	and MGM_BG_10( ZN_row5, A2_inv_for_AOI222_X4_7T5P0, B1_inv_for_AOI222_X4_7T5P0, C1_inv_for_AOI222_X4_7T5P0 );

	wire ZN_row6;

	and MGM_BG_11( ZN_row6, A2_inv_for_AOI222_X4_7T5P0, B1_inv_for_AOI222_X4_7T5P0, C2_inv_for_AOI222_X4_7T5P0 );

	wire ZN_row7;

	and MGM_BG_12( ZN_row7, A2_inv_for_AOI222_X4_7T5P0, B2_inv_for_AOI222_X4_7T5P0, C1_inv_for_AOI222_X4_7T5P0 );

	wire ZN_row8;

	and MGM_BG_13( ZN_row8, A2_inv_for_AOI222_X4_7T5P0, B2_inv_for_AOI222_X4_7T5P0, C2_inv_for_AOI222_X4_7T5P0 );

	or MGM_BG_14( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4, ZN_row5, ZN_row6, ZN_row7, ZN_row8 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI22_X1_7T5P0_func( B2, B1, ZN, A1, A2, VDD, VSS );
input A1, A2, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI22_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI22_X1_7T5P0, A1 );

	wire B1_inv_for_AOI22_X1_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI22_X1_7T5P0, B1 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_AOI22_X1_7T5P0, B1_inv_for_AOI22_X1_7T5P0 );

	wire B2_inv_for_AOI22_X1_7T5P0;

	not MGM_BG_3( B2_inv_for_AOI22_X1_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_4( ZN_row2, A1_inv_for_AOI22_X1_7T5P0, B2_inv_for_AOI22_X1_7T5P0 );

	wire A2_inv_for_AOI22_X1_7T5P0;

	not MGM_BG_5( A2_inv_for_AOI22_X1_7T5P0, A2 );

	wire ZN_row3;

	and MGM_BG_6( ZN_row3, A2_inv_for_AOI22_X1_7T5P0, B1_inv_for_AOI22_X1_7T5P0 );

	wire ZN_row4;

	and MGM_BG_7( ZN_row4, A2_inv_for_AOI22_X1_7T5P0, B2_inv_for_AOI22_X1_7T5P0 );

	or MGM_BG_8( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI22_X2_7T5P0_func( B2, B1, ZN, A2, A1, VDD, VSS );
input A1, A2, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI22_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI22_X2_7T5P0, A1 );

	wire B1_inv_for_AOI22_X2_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI22_X2_7T5P0, B1 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_AOI22_X2_7T5P0, B1_inv_for_AOI22_X2_7T5P0 );

	wire B2_inv_for_AOI22_X2_7T5P0;

	not MGM_BG_3( B2_inv_for_AOI22_X2_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_4( ZN_row2, A1_inv_for_AOI22_X2_7T5P0, B2_inv_for_AOI22_X2_7T5P0 );

	wire A2_inv_for_AOI22_X2_7T5P0;

	not MGM_BG_5( A2_inv_for_AOI22_X2_7T5P0, A2 );

	wire ZN_row3;

	and MGM_BG_6( ZN_row3, A2_inv_for_AOI22_X2_7T5P0, B1_inv_for_AOI22_X2_7T5P0 );

	wire ZN_row4;

	and MGM_BG_7( ZN_row4, A2_inv_for_AOI22_X2_7T5P0, B2_inv_for_AOI22_X2_7T5P0 );

	or MGM_BG_8( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module AOI22_X4_7T5P0_func( B2, B1, ZN, A2, A1, VDD, VSS );
input A1, A2, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_AOI22_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_AOI22_X4_7T5P0, A1 );

	wire B1_inv_for_AOI22_X4_7T5P0;

	not MGM_BG_1( B1_inv_for_AOI22_X4_7T5P0, B1 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_AOI22_X4_7T5P0, B1_inv_for_AOI22_X4_7T5P0 );

	wire B2_inv_for_AOI22_X4_7T5P0;

	not MGM_BG_3( B2_inv_for_AOI22_X4_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_4( ZN_row2, A1_inv_for_AOI22_X4_7T5P0, B2_inv_for_AOI22_X4_7T5P0 );

	wire A2_inv_for_AOI22_X4_7T5P0;

	not MGM_BG_5( A2_inv_for_AOI22_X4_7T5P0, A2 );

	wire ZN_row3;

	and MGM_BG_6( ZN_row3, A2_inv_for_AOI22_X4_7T5P0, B1_inv_for_AOI22_X4_7T5P0 );

	wire ZN_row4;

	and MGM_BG_7( ZN_row4, A2_inv_for_AOI22_X4_7T5P0, B2_inv_for_AOI22_X4_7T5P0 );

	or MGM_BG_8( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUFZ_X12_7T5P0_func( EN, I, Z, VDD, VSS );
input EN, I;
inout VDD, VSS;
output Z;

	wire MGM_WB_0;

	wire MGM_WB_1;

	and MGM_BG_0( MGM_WB_0, EN, I );

	not MGM_BG_1( MGM_WB_1, EN );

	bufif0 MGM_BG_2( Z, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUFZ_X16_7T5P0_func( EN, I, Z, VDD, VSS );
input EN, I;
inout VDD, VSS;
output Z;

	wire MGM_WB_0;

	wire MGM_WB_1;

	and MGM_BG_0( MGM_WB_0, EN, I );

	not MGM_BG_1( MGM_WB_1, EN );

	bufif0 MGM_BG_2( Z, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUFZ_X1_7T5P0_func( EN, I, Z, VDD, VSS );
input EN, I;
inout VDD, VSS;
output Z;

	wire MGM_WB_0;

	wire MGM_WB_1;

	and MGM_BG_0( MGM_WB_0, EN, I );

	not MGM_BG_1( MGM_WB_1, EN );

	bufif0 MGM_BG_2( Z, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUFZ_X2_7T5P0_func( EN, I, Z, VDD, VSS );
input EN, I;
inout VDD, VSS;
output Z;

	wire MGM_WB_0;

	wire MGM_WB_1;

	and MGM_BG_0( MGM_WB_0, EN, I );

	not MGM_BG_1( MGM_WB_1, EN );

	bufif0 MGM_BG_2( Z, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUFZ_X3_7T5P0_func( EN, I, Z, VDD, VSS );
input EN, I;
inout VDD, VSS;
output Z;

	wire MGM_WB_0;

	wire MGM_WB_1;

	and MGM_BG_0( MGM_WB_0, EN, I );

	not MGM_BG_1( MGM_WB_1, EN );

	bufif0 MGM_BG_2( Z, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUFZ_X4_7T5P0_func( EN, I, Z, VDD, VSS );
input EN, I;
inout VDD, VSS;
output Z;

	wire MGM_WB_0;

	wire MGM_WB_1;

	and MGM_BG_0( MGM_WB_0, EN, I );

	not MGM_BG_1( MGM_WB_1, EN );

	bufif0 MGM_BG_2( Z, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUFZ_X8_7T5P0_func( EN, I, Z, VDD, VSS );
input EN, I;
inout VDD, VSS;
output Z;

	wire MGM_WB_0;

	wire MGM_WB_1;

	and MGM_BG_0( MGM_WB_0, EN, I );

	not MGM_BG_1( MGM_WB_1, EN );

	bufif0 MGM_BG_2( Z, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUF_X12_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUF_X16_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUF_X1_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUF_X20_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUF_X2_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUF_X3_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUF_X4_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module BUF_X8_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKBUF_X12_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKBUF_X16_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKBUF_X1_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKBUF_X20_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKBUF_X2_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKBUF_X3_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKBUF_X4_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKBUF_X8_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKINV_X12_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKINV_X16_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKINV_X1_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKINV_X20_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKINV_X2_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKINV_X3_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKINV_X4_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module CLKINV_X8_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


primitive UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( Q, C, P, CK, D, N );
output Q;
reg Q;
input C, P, CK, D, N; 
table 
//C  P  CK  D  N   : Q : Q 
  0  0  n  ?  ?  :  ?  :  -;
  ?  0  r  0  ?  :  ?  :  0;
  ?  0  p  0  ?  :  0  :  0;
  1  0  ?  ?  ?  :  ?  :  0;
  0  ?  r  1  ?  :  ?  :  1;
  0  ?  p  1  ?  :  1  :  1;
  0  1  ?  ?  ?  :  ?  :  1;
  ?  ?  ?  ?  *  :  ?  :  x;
  0  0  ?  *  ?  :  ?  :  -;
  0  n  ?  ?  ?  :  ?  :  -;
  n  0  ?  ?  ?  :  ?  :  -;
  0  p  ?  ?  ?  :  ?  :  -;
                  
endtable
endprimitive


`celldefine
module DFFNQ_X1_7T5P0_func( CLKN, D, Q, VDD, VSS, notifier );
input CLKN, D, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNQ_X2_7T5P0_func( CLKN, D, Q, VDD, VSS, notifier );
input CLKN, D, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNQ_X4_7T5P0_func( CLKN, D, Q, VDD, VSS, notifier );
input CLKN, D, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNRNQ_X1_7T5P0_func( CLKN, D, RN, Q, VDD, VSS, notifier );
input CLKN, D, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_P0, RN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNRNQ_X2_7T5P0_func( CLKN, D, RN, Q, VDD, VSS, notifier );
input CLKN, D, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_P0, RN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNRNQ_X4_7T5P0_func( CLKN, D, RN, Q, VDD, VSS, notifier );
input CLKN, D, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_P0, RN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


primitive UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( Q, C, P, CK, D, N );
output Q;
reg Q;
input C, P, CK, D, N; 
table 
//C  P  CK  D  N   : Q : Q 
  0  0  n  ?  ?  :  ?  :  -;
  ?  0  r  0  ?  :  ?  :  0;
  ?  0  p  0  ?  :  0  :  0;
  1  0  ?  ?  ?  :  ?  :  0;
  0  ?  r  1  ?  :  ?  :  1;
  0  ?  p  1  ?  :  1  :  1;
  ?  1  ?  ?  ?  :  ?  :  1;
  0  0  ?  *  ?  :  ?  :  -;
  ?  ?  ?  ?  *  :  ?  :  x;
  0  n  ?  ?  ?  :  ?  :  -;
  n  0  ?  ?  ?  :  ?  :  -;
  0  p  ?  ?  ?  :  ?  :  -;
                  
endtable
endprimitive


`celldefine
module DFFNRSNQ_X1_7T5P0_func( CLKN, D, SETN, RN, Q, VDD, VSS, notifier );
input CLKN, D, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_P0, RN );

	not MGM_BG_2( MGM_C0, SETN );

	not MGM_BG_3( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_4( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNRSNQ_X2_7T5P0_func( CLKN, D, SETN, RN, Q, VDD, VSS, notifier );
input CLKN, D, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_P0, RN );

	not MGM_BG_2( MGM_C0, SETN );

	not MGM_BG_3( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_4( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNRSNQ_X4_7T5P0_func( CLKN, D, SETN, RN, Q, VDD, VSS, notifier );
input CLKN, D, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_P0, RN );

	not MGM_BG_2( MGM_C0, SETN );

	not MGM_BG_3( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_4( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNSNQ_X1_7T5P0_func( CLKN, D, SETN, Q, VDD, VSS, notifier );
input CLKN, D, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_C0, SETN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNSNQ_X2_7T5P0_func( CLKN, D, SETN, Q, VDD, VSS, notifier );
input CLKN, D, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_C0, SETN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFNSNQ_X4_7T5P0_func( CLKN, D, SETN, Q, VDD, VSS, notifier );
input CLKN, D, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_CLK0, CLKN );

	not MGM_BG_1( MGM_C0, SETN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, MGM_CLK0, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFQ_X1_7T5P0_func( CLK, D, Q, VDD, VSS, notifier );
input CLK, D, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_1( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFQ_X2_7T5P0_func( CLK, D, Q, VDD, VSS, notifier );
input CLK, D, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_1( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFQ_X4_7T5P0_func( CLK, D, Q, VDD, VSS, notifier );
input CLK, D, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_1( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFRNQ_X1_7T5P0_func( CLK, D, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFRNQ_X2_7T5P0_func( CLK, D, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFRNQ_X4_7T5P0_func( CLK, D, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFRSNQ_X1_7T5P0_func( CLK, D, SETN, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_C0, SETN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFRSNQ_X2_7T5P0_func( CLK, D, SETN, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_C0, SETN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFRSNQ_X4_7T5P0_func( CLK, D, SETN, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_C0, SETN );

	not MGM_BG_2( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_3( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFSNQ_X1_7T5P0_func( CLK, D, SETN, Q, VDD, VSS, notifier );
input CLK, D, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, SETN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFSNQ_X2_7T5P0_func( CLK, D, SETN, Q, VDD, VSS, notifier );
input CLK, D, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, SETN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DFFSNQ_X4_7T5P0_func( CLK, D, SETN, Q, VDD, VSS, notifier );
input CLK, D, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, SETN );

	not MGM_BG_1( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_2( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYA_X1_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYA_X2_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYA_X4_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYB_X1_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYB_X2_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYB_X4_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYC_X1_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYC_X2_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYC_X4_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYD_X1_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYD_X2_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module DLYD_X4_7T5P0_func( I, Z, VDD, VSS );
input I;
inout VDD, VSS;
output Z;

	buf MGM_BG_0( Z, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ENDCAP_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILLCAP_X16_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILLCAP_X32_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILLCAP_X4_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILLCAP_X64_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILLCAP_X8_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILLTIE_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILL_X16_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILL_X1_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILL_X2_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILL_X32_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILL_X4_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILL_X64_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module FILL_X8_7T5P0_func( VDD, VSS );
inout VDD, VSS;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module HOLD_7T5P0_func( Z, VDD, VSS );
inout VDD, VSS;
inout Z;

	buf (weak0, weak1) MGM_BG_0( Z, MGM_WB_0 );

	buf MGM_BG_1( MGM_WB_0, Z );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


primitive UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( Q, C, P, CK, D, N );
output Q;
reg Q;
input C, P, CK, D, N; 
table 
//C  P  CK  D  N   : Q : Q 
  0  0  0  *  ?  :  ?  :  -;
  0  0  (?0)  ?  ?  :  ?  :  -;
  0  (?0)  0  ?  ?  :  ?  :  -;
  (?0)  0  0  ?  ?  :  ?  :  -;
  ?  0  1  0  ?  :  ?  :  0;
  ?  0  ?  (?0)  ?  :  0  :  0;
  ?  (?0)  ?  0  ?  :  0  :  0;
  1  0  ?  ?  ?  :  ?  :  0;
  0  ?  1  1  ?  :  ?  :  1;
  0  ?  ?  (?1)  ?  :  1  :  1;
  (?0)  ?  ?  1  ?  :  1  :  1;
  0  1  ?  ?  ?  :  ?  :  1;
  ?  ?  ?  ?  *  :  ?  :  x;

endtable
endprimitive


`celldefine
module ICGTN_X1_7T5P0_func( TE, E, CLKN, Q, VDD, VSS, notifier );
input CLKN, E, TE, VDD, VSS, notifier;
output Q;

	or MGM_BG_0( MGM_D0, E, TE );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ3, 1'b0, 1'b0, CLKN, MGM_D0, notifier );

	wire IQ3_inv_for_ICGTN_X1_7T5P0;

	not MGM_BG_1( IQ3_inv_for_ICGTN_X1_7T5P0, IQ3 );

	or MGM_BG_2( Q, CLKN, IQ3_inv_for_ICGTN_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ICGTN_X2_7T5P0_func( TE, E, CLKN, Q, VDD, VSS, notifier );
input CLKN, E, TE, VDD, VSS, notifier;
output Q;

	or MGM_BG_0( MGM_D0, E, TE );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ3, 1'b0, 1'b0, CLKN, MGM_D0, notifier );

	wire IQ3_inv_for_ICGTN_X2_7T5P0;

	not MGM_BG_1( IQ3_inv_for_ICGTN_X2_7T5P0, IQ3 );

	or MGM_BG_2( Q, CLKN, IQ3_inv_for_ICGTN_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ICGTN_X4_7T5P0_func( TE, E, CLKN, Q, VDD, VSS, notifier );
input CLKN, E, TE, VDD, VSS, notifier;
output Q;

	or MGM_BG_0( MGM_D0, E, TE );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ3, 1'b0, 1'b0, CLKN, MGM_D0, notifier );

	wire IQ3_inv_for_ICGTN_X4_7T5P0;

	not MGM_BG_1( IQ3_inv_for_ICGTN_X4_7T5P0, IQ3 );

	or MGM_BG_2( Q, CLKN, IQ3_inv_for_ICGTN_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ICGTP_X1_7T5P0_func( TE, E, CLK, Q, VDD, VSS, notifier );
input CLK, E, TE, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_EN0, CLK );

	or MGM_BG_1( MGM_D0, E, TE );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, 1'b0, MGM_EN0, MGM_D0, notifier );

	and MGM_BG_2( Q, CLK, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ICGTP_X2_7T5P0_func( TE, E, CLK, Q, VDD, VSS, notifier );
input CLK, E, TE, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_EN0, CLK );

	or MGM_BG_1( MGM_D0, E, TE );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, 1'b0, MGM_EN0, MGM_D0, notifier );

	and MGM_BG_2( Q, CLK, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module ICGTP_X4_7T5P0_func( TE, E, CLK, Q, VDD, VSS, notifier );
input CLK, E, TE, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_EN0, CLK );

	or MGM_BG_1( MGM_D0, E, TE );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, 1'b0, MGM_EN0, MGM_D0, notifier );

	and MGM_BG_2( Q, CLK, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INVZ_X12_7T5P0_func( EN, I, ZN, VDD, VSS );
input EN, I;
inout VDD, VSS;
output ZN;

	wire MGM_WB_0;

	wire MGM_WB_1;

	wire I_inv_for_INVZ_X12_7T5P0;

	not MGM_BG_0( I_inv_for_INVZ_X12_7T5P0, I );

	and MGM_BG_1( MGM_WB_0, I_inv_for_INVZ_X12_7T5P0, EN );

	not MGM_BG_2( MGM_WB_1, EN );

	bufif0 MGM_BG_3( ZN, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INVZ_X16_7T5P0_func( EN, I, ZN, VDD, VSS );
input EN, I;
inout VDD, VSS;
output ZN;

	wire MGM_WB_0;

	wire MGM_WB_1;

	wire I_inv_for_INVZ_X16_7T5P0;

	not MGM_BG_0( I_inv_for_INVZ_X16_7T5P0, I );

	and MGM_BG_1( MGM_WB_0, I_inv_for_INVZ_X16_7T5P0, EN );

	not MGM_BG_2( MGM_WB_1, EN );

	bufif0 MGM_BG_3( ZN, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INVZ_X1_7T5P0_func( EN, ZN, I, VDD, VSS );
input EN, I;
inout VDD, VSS;
output ZN;

	wire MGM_WB_0;

	wire MGM_WB_1;

	wire I_inv_for_INVZ_X1_7T5P0;

	not MGM_BG_0( I_inv_for_INVZ_X1_7T5P0, I );

	and MGM_BG_1( MGM_WB_0, I_inv_for_INVZ_X1_7T5P0, EN );

	not MGM_BG_2( MGM_WB_1, EN );

	bufif0 MGM_BG_3( ZN, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INVZ_X2_7T5P0_func( EN, ZN, I, VDD, VSS );
input EN, I;
inout VDD, VSS;
output ZN;

	wire MGM_WB_0;

	wire MGM_WB_1;

	wire I_inv_for_INVZ_X2_7T5P0;

	not MGM_BG_0( I_inv_for_INVZ_X2_7T5P0, I );

	and MGM_BG_1( MGM_WB_0, I_inv_for_INVZ_X2_7T5P0, EN );

	not MGM_BG_2( MGM_WB_1, EN );

	bufif0 MGM_BG_3( ZN, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INVZ_X3_7T5P0_func( EN, I, ZN, VDD, VSS );
input EN, I;
inout VDD, VSS;
output ZN;

	wire MGM_WB_0;

	wire MGM_WB_1;

	wire I_inv_for_INVZ_X3_7T5P0;

	not MGM_BG_0( I_inv_for_INVZ_X3_7T5P0, I );

	and MGM_BG_1( MGM_WB_0, I_inv_for_INVZ_X3_7T5P0, EN );

	not MGM_BG_2( MGM_WB_1, EN );

	bufif0 MGM_BG_3( ZN, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INVZ_X4_7T5P0_func( EN, I, ZN, VDD, VSS );
input EN, I;
inout VDD, VSS;
output ZN;

	wire MGM_WB_0;

	wire MGM_WB_1;

	wire I_inv_for_INVZ_X4_7T5P0;

	not MGM_BG_0( I_inv_for_INVZ_X4_7T5P0, I );

	and MGM_BG_1( MGM_WB_0, I_inv_for_INVZ_X4_7T5P0, EN );

	not MGM_BG_2( MGM_WB_1, EN );

	bufif0 MGM_BG_3( ZN, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INVZ_X8_7T5P0_func( EN, I, ZN, VDD, VSS );
input EN, I;
inout VDD, VSS;
output ZN;

	wire MGM_WB_0;

	wire MGM_WB_1;

	wire I_inv_for_INVZ_X8_7T5P0;

	not MGM_BG_0( I_inv_for_INVZ_X8_7T5P0, I );

	and MGM_BG_1( MGM_WB_0, I_inv_for_INVZ_X8_7T5P0, EN );

	not MGM_BG_2( MGM_WB_1, EN );

	bufif0 MGM_BG_3( ZN, MGM_WB_0,MGM_WB_1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INV_X12_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INV_X16_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INV_X1_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INV_X20_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INV_X2_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INV_X3_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INV_X4_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module INV_X8_7T5P0_func( I, ZN, VDD, VSS );
input I;
inout VDD, VSS;
output ZN;

	not MGM_BG_0( ZN, I );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATQ_X1_7T5P0_func( E, D, Q, VDD, VSS, notifier );
input D, E, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ1, 1'b0, 1'b0, E, MGM_D0, notifier );

	not MGM_BG_1( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATQ_X2_7T5P0_func( E, D, Q, VDD, VSS, notifier );
input D, E, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ1, 1'b0, 1'b0, E, MGM_D0, notifier );

	not MGM_BG_1( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATQ_X4_7T5P0_func( E, D, Q, VDD, VSS, notifier );
input D, E, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_D0, D );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ1, 1'b0, 1'b0, E, MGM_D0, notifier );

	not MGM_BG_1( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATRNQ_X1_7T5P0_func( E, D, RN, Q, VDD, VSS, notifier );
input D, E, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, RN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, MGM_C0, 1'b0, E, D, notifier );

	buf MGM_BG_1( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATRNQ_X2_7T5P0_func( E, D, RN, Q, VDD, VSS, notifier );
input D, E, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, RN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, MGM_C0, 1'b0, E, D, notifier );

	buf MGM_BG_1( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATRNQ_X4_7T5P0_func( E, D, RN, Q, VDD, VSS, notifier );
input D, E, RN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, RN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, MGM_C0, 1'b0, E, D, notifier );

	buf MGM_BG_1( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


primitive UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_LATCH_UDP( Q, C, P, CK, D, N );
output Q;
reg Q;
input C, P, CK, D, N; 
table 
//C  P  CK  D  N   : Q : Q 
  0  0  0  *  ?  :  ?  :  -;
  0  0  (?0)  ?  ?  :  ?  :  -;
  0  (?0)  0  ?  ?  :  ?  :  -;
  (?0)  0  0  ?  ?  :  ?  :  -;
  ?  0  1  0  ?  :  ?  :  0;
  ?  0  ?  (?0)  ?  :  0  :  0;
  ?  (?0)  ?  0  ?  :  0  :  0;
  1  0  ?  ?  ?  :  ?  :  0;
  0  ?  1  1  ?  :  ?  :  1;
  0  ?  ?  (?1)  ?  :  1  :  1;
  (?0)  ?  ?  1  ?  :  1  :  1;
  ?  1  ?  ?  ?  :  ?  :  1;
  ?  ?  ?  ?  *  :  ?  :  x;

endtable
endprimitive


`celldefine
module LATRSNQ_X1_7T5P0_func( E, D, RN, SETN, Q, VDD, VSS, notifier );
input D, E, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, SETN );

	not MGM_BG_1( MGM_C0, RN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_LATCH_UDP( IQ2, MGM_C0, MGM_P0, E, D, notifier );

	buf MGM_BG_2( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATRSNQ_X2_7T5P0_func( E, D, RN, SETN, Q, VDD, VSS, notifier );
input D, E, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, SETN );

	not MGM_BG_1( MGM_C0, RN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_LATCH_UDP( IQ2, MGM_C0, MGM_P0, E, D, notifier );

	buf MGM_BG_2( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATRSNQ_X4_7T5P0_func( E, D, RN, SETN, Q, VDD, VSS, notifier );
input D, E, RN, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, SETN );

	not MGM_BG_1( MGM_C0, RN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_LATCH_UDP( IQ2, MGM_C0, MGM_P0, E, D, notifier );

	buf MGM_BG_2( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATSNQ_X1_7T5P0_func( E, D, SETN, Q, VDD, VSS, notifier );
input D, E, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, SETN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, MGM_P0, E, D, notifier );

	buf MGM_BG_1( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATSNQ_X2_7T5P0_func( E, D, SETN, Q, VDD, VSS, notifier );
input D, E, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, SETN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, MGM_P0, E, D, notifier );

	buf MGM_BG_1( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module LATSNQ_X4_7T5P0_func( E, D, SETN, Q, VDD, VSS, notifier );
input D, E, SETN, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, SETN );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_LATCH_UDP( IQ2, 1'b0, MGM_P0, E, D, notifier );

	buf MGM_BG_1( Q, IQ2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module MUX2_X1_7T5P0_func( Z, I1, S, I0, VDD, VSS );
input I0, I1, S;
inout VDD, VSS;
output Z;

	wire Z_row1;

	and MGM_BG_0( Z_row1, I0, I1 );

	wire S_inv_for_MUX2_X1_7T5P0;

	not MGM_BG_1( S_inv_for_MUX2_X1_7T5P0, S );

	wire Z_row2;

	and MGM_BG_2( Z_row2, S_inv_for_MUX2_X1_7T5P0, I0 );

	wire Z_row3;

	and MGM_BG_3( Z_row3, I1, S );

	or MGM_BG_4( Z, Z_row1, Z_row2, Z_row3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module MUX2_X2_7T5P0_func( Z, I1, S, I0, VDD, VSS );
input I0, I1, S;
inout VDD, VSS;
output Z;

	wire Z_row1;

	and MGM_BG_0( Z_row1, I0, I1 );

	wire S_inv_for_MUX2_X2_7T5P0;

	not MGM_BG_1( S_inv_for_MUX2_X2_7T5P0, S );

	wire Z_row2;

	and MGM_BG_2( Z_row2, S_inv_for_MUX2_X2_7T5P0, I0 );

	wire Z_row3;

	and MGM_BG_3( Z_row3, I1, S );

	or MGM_BG_4( Z, Z_row1, Z_row2, Z_row3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module MUX2_X4_7T5P0_func( Z, I1, S, I0, VDD, VSS );
input I0, I1, S;
inout VDD, VSS;
output Z;

	wire Z_row1;

	and MGM_BG_0( Z_row1, I0, I1 );

	wire S_inv_for_MUX2_X4_7T5P0;

	not MGM_BG_1( S_inv_for_MUX2_X4_7T5P0, S );

	wire Z_row2;

	and MGM_BG_2( Z_row2, S_inv_for_MUX2_X4_7T5P0, I0 );

	wire Z_row3;

	and MGM_BG_3( Z_row3, I1, S );

	or MGM_BG_4( Z, Z_row1, Z_row2, Z_row3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module MUX4_X1_7T5P0_func( I2, S0, I3, Z, S1, I1, I0, VDD, VSS );
input I0, I1, I2, I3, S0, S1;
inout VDD, VSS;
output Z;

	wire S0_inv_for_MUX4_X1_7T5P0;

	not MGM_BG_0( S0_inv_for_MUX4_X1_7T5P0, S0 );

	wire S1_inv_for_MUX4_X1_7T5P0;

	not MGM_BG_1( S1_inv_for_MUX4_X1_7T5P0, S1 );

	wire Z_row1;

	and MGM_BG_2( Z_row1, S0_inv_for_MUX4_X1_7T5P0, S1_inv_for_MUX4_X1_7T5P0, I0 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, S1_inv_for_MUX4_X1_7T5P0, I1, S0 );

	wire Z_row3;

	and MGM_BG_4( Z_row3, S0_inv_for_MUX4_X1_7T5P0, I2, S1 );

	wire Z_row4;

	and MGM_BG_5( Z_row4, I3, S0, S1 );

	or MGM_BG_6( Z, Z_row1, Z_row2, Z_row3, Z_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module MUX4_X2_7T5P0_func( I2, S0, I3, Z, S1, I1, I0, VDD, VSS );
input I0, I1, I2, I3, S0, S1;
inout VDD, VSS;
output Z;

	wire S0_inv_for_MUX4_X2_7T5P0;

	not MGM_BG_0( S0_inv_for_MUX4_X2_7T5P0, S0 );

	wire S1_inv_for_MUX4_X2_7T5P0;

	not MGM_BG_1( S1_inv_for_MUX4_X2_7T5P0, S1 );

	wire Z_row1;

	and MGM_BG_2( Z_row1, S0_inv_for_MUX4_X2_7T5P0, S1_inv_for_MUX4_X2_7T5P0, I0 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, S1_inv_for_MUX4_X2_7T5P0, I1, S0 );

	wire Z_row3;

	and MGM_BG_4( Z_row3, S0_inv_for_MUX4_X2_7T5P0, I2, S1 );

	wire Z_row4;

	and MGM_BG_5( Z_row4, I3, S0, S1 );

	or MGM_BG_6( Z, Z_row1, Z_row2, Z_row3, Z_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module MUX4_X4_7T5P0_func( I2, S0, I3, Z, S1, I1, I0, VDD, VSS );
input I0, I1, I2, I3, S0, S1;
inout VDD, VSS;
output Z;

	wire S0_inv_for_MUX4_X4_7T5P0;

	not MGM_BG_0( S0_inv_for_MUX4_X4_7T5P0, S0 );

	wire S1_inv_for_MUX4_X4_7T5P0;

	not MGM_BG_1( S1_inv_for_MUX4_X4_7T5P0, S1 );

	wire Z_row1;

	and MGM_BG_2( Z_row1, S0_inv_for_MUX4_X4_7T5P0, S1_inv_for_MUX4_X4_7T5P0, I0 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, S1_inv_for_MUX4_X4_7T5P0, I1, S0 );

	wire Z_row3;

	and MGM_BG_4( Z_row3, S0_inv_for_MUX4_X4_7T5P0, I2, S1 );

	wire Z_row4;

	and MGM_BG_5( Z_row4, I3, S0, S1 );

	or MGM_BG_6( Z, Z_row1, Z_row2, Z_row3, Z_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND2_X1_7T5P0_func( A2, A1, ZN, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND2_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND2_X1_7T5P0, A1 );

	wire A2_inv_for_NAND2_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND2_X1_7T5P0, A2 );

	or MGM_BG_2( ZN, A1_inv_for_NAND2_X1_7T5P0, A2_inv_for_NAND2_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND2_X2_7T5P0_func( A1, A2, ZN, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND2_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND2_X2_7T5P0, A1 );

	wire A2_inv_for_NAND2_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND2_X2_7T5P0, A2 );

	or MGM_BG_2( ZN, A1_inv_for_NAND2_X2_7T5P0, A2_inv_for_NAND2_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND2_X4_7T5P0_func( A1, A2, ZN, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND2_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND2_X4_7T5P0, A1 );

	wire A2_inv_for_NAND2_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND2_X4_7T5P0, A2 );

	or MGM_BG_2( ZN, A1_inv_for_NAND2_X4_7T5P0, A2_inv_for_NAND2_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND3_X1_7T5P0_func( A3, ZN, A2, A1, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND3_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND3_X1_7T5P0, A1 );

	wire A2_inv_for_NAND3_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND3_X1_7T5P0, A2 );

	wire A3_inv_for_NAND3_X1_7T5P0;

	not MGM_BG_2( A3_inv_for_NAND3_X1_7T5P0, A3 );

	or MGM_BG_3( ZN, A1_inv_for_NAND3_X1_7T5P0, A2_inv_for_NAND3_X1_7T5P0, A3_inv_for_NAND3_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND3_X2_7T5P0_func( ZN, A3, A2, A1, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND3_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND3_X2_7T5P0, A1 );

	wire A2_inv_for_NAND3_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND3_X2_7T5P0, A2 );

	wire A3_inv_for_NAND3_X2_7T5P0;

	not MGM_BG_2( A3_inv_for_NAND3_X2_7T5P0, A3 );

	or MGM_BG_3( ZN, A1_inv_for_NAND3_X2_7T5P0, A2_inv_for_NAND3_X2_7T5P0, A3_inv_for_NAND3_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND3_X4_7T5P0_func( A2, ZN, A3, A1, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND3_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND3_X4_7T5P0, A1 );

	wire A2_inv_for_NAND3_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND3_X4_7T5P0, A2 );

	wire A3_inv_for_NAND3_X4_7T5P0;

	not MGM_BG_2( A3_inv_for_NAND3_X4_7T5P0, A3 );

	or MGM_BG_3( ZN, A1_inv_for_NAND3_X4_7T5P0, A2_inv_for_NAND3_X4_7T5P0, A3_inv_for_NAND3_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND4_X1_7T5P0_func( A4, ZN, A3, A2, A1, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND4_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND4_X1_7T5P0, A1 );

	wire A2_inv_for_NAND4_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND4_X1_7T5P0, A2 );

	wire A3_inv_for_NAND4_X1_7T5P0;

	not MGM_BG_2( A3_inv_for_NAND4_X1_7T5P0, A3 );

	wire A4_inv_for_NAND4_X1_7T5P0;

	not MGM_BG_3( A4_inv_for_NAND4_X1_7T5P0, A4 );

	or MGM_BG_4( ZN, A1_inv_for_NAND4_X1_7T5P0, A2_inv_for_NAND4_X1_7T5P0, A3_inv_for_NAND4_X1_7T5P0, A4_inv_for_NAND4_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND4_X2_7T5P0_func( ZN, A3, A1, A4, A2, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND4_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND4_X2_7T5P0, A1 );

	wire A2_inv_for_NAND4_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND4_X2_7T5P0, A2 );

	wire A3_inv_for_NAND4_X2_7T5P0;

	not MGM_BG_2( A3_inv_for_NAND4_X2_7T5P0, A3 );

	wire A4_inv_for_NAND4_X2_7T5P0;

	not MGM_BG_3( A4_inv_for_NAND4_X2_7T5P0, A4 );

	or MGM_BG_4( ZN, A1_inv_for_NAND4_X2_7T5P0, A2_inv_for_NAND4_X2_7T5P0, A3_inv_for_NAND4_X2_7T5P0, A4_inv_for_NAND4_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NAND4_X4_7T5P0_func( A3, ZN, A4, A1, A2, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NAND4_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_NAND4_X4_7T5P0, A1 );

	wire A2_inv_for_NAND4_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_NAND4_X4_7T5P0, A2 );

	wire A3_inv_for_NAND4_X4_7T5P0;

	not MGM_BG_2( A3_inv_for_NAND4_X4_7T5P0, A3 );

	wire A4_inv_for_NAND4_X4_7T5P0;

	not MGM_BG_3( A4_inv_for_NAND4_X4_7T5P0, A4 );

	or MGM_BG_4( ZN, A1_inv_for_NAND4_X4_7T5P0, A2_inv_for_NAND4_X4_7T5P0, A3_inv_for_NAND4_X4_7T5P0, A4_inv_for_NAND4_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR2_X1_7T5P0_func( A2, ZN, A1, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR2_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR2_X1_7T5P0, A1 );

	wire A2_inv_for_NOR2_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR2_X1_7T5P0, A2 );

	and MGM_BG_2( ZN, A1_inv_for_NOR2_X1_7T5P0, A2_inv_for_NOR2_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR2_X2_7T5P0_func( A2, ZN, A1, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR2_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR2_X2_7T5P0, A1 );

	wire A2_inv_for_NOR2_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR2_X2_7T5P0, A2 );

	and MGM_BG_2( ZN, A1_inv_for_NOR2_X2_7T5P0, A2_inv_for_NOR2_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR2_X4_7T5P0_func( ZN, A2, A1, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR2_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR2_X4_7T5P0, A1 );

	wire A2_inv_for_NOR2_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR2_X4_7T5P0, A2 );

	and MGM_BG_2( ZN, A1_inv_for_NOR2_X4_7T5P0, A2_inv_for_NOR2_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR3_X1_7T5P0_func( A3, ZN, A2, A1, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR3_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR3_X1_7T5P0, A1 );

	wire A2_inv_for_NOR3_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR3_X1_7T5P0, A2 );

	wire A3_inv_for_NOR3_X1_7T5P0;

	not MGM_BG_2( A3_inv_for_NOR3_X1_7T5P0, A3 );

	and MGM_BG_3( ZN, A1_inv_for_NOR3_X1_7T5P0, A2_inv_for_NOR3_X1_7T5P0, A3_inv_for_NOR3_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR3_X2_7T5P0_func( ZN, A3, A2, A1, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR3_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR3_X2_7T5P0, A1 );

	wire A2_inv_for_NOR3_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR3_X2_7T5P0, A2 );

	wire A3_inv_for_NOR3_X2_7T5P0;

	not MGM_BG_2( A3_inv_for_NOR3_X2_7T5P0, A3 );

	and MGM_BG_3( ZN, A1_inv_for_NOR3_X2_7T5P0, A2_inv_for_NOR3_X2_7T5P0, A3_inv_for_NOR3_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR3_X4_7T5P0_func( A2, ZN, A3, A1, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR3_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR3_X4_7T5P0, A1 );

	wire A2_inv_for_NOR3_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR3_X4_7T5P0, A2 );

	wire A3_inv_for_NOR3_X4_7T5P0;

	not MGM_BG_2( A3_inv_for_NOR3_X4_7T5P0, A3 );

	and MGM_BG_3( ZN, A1_inv_for_NOR3_X4_7T5P0, A2_inv_for_NOR3_X4_7T5P0, A3_inv_for_NOR3_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR4_X1_7T5P0_func( A4, ZN, A3, A2, A1, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR4_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR4_X1_7T5P0, A1 );

	wire A2_inv_for_NOR4_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR4_X1_7T5P0, A2 );

	wire A3_inv_for_NOR4_X1_7T5P0;

	not MGM_BG_2( A3_inv_for_NOR4_X1_7T5P0, A3 );

	wire A4_inv_for_NOR4_X1_7T5P0;

	not MGM_BG_3( A4_inv_for_NOR4_X1_7T5P0, A4 );

	and MGM_BG_4( ZN, A1_inv_for_NOR4_X1_7T5P0, A2_inv_for_NOR4_X1_7T5P0, A3_inv_for_NOR4_X1_7T5P0, A4_inv_for_NOR4_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR4_X2_7T5P0_func( A4, A3, ZN, A2, A1, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR4_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR4_X2_7T5P0, A1 );

	wire A2_inv_for_NOR4_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR4_X2_7T5P0, A2 );

	wire A3_inv_for_NOR4_X2_7T5P0;

	not MGM_BG_2( A3_inv_for_NOR4_X2_7T5P0, A3 );

	wire A4_inv_for_NOR4_X2_7T5P0;

	not MGM_BG_3( A4_inv_for_NOR4_X2_7T5P0, A4 );

	and MGM_BG_4( ZN, A1_inv_for_NOR4_X2_7T5P0, A2_inv_for_NOR4_X2_7T5P0, A3_inv_for_NOR4_X2_7T5P0, A4_inv_for_NOR4_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module NOR4_X4_7T5P0_func( A4, A3, ZN, A2, A1, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_NOR4_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_NOR4_X4_7T5P0, A1 );

	wire A2_inv_for_NOR4_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_NOR4_X4_7T5P0, A2 );

	wire A3_inv_for_NOR4_X4_7T5P0;

	not MGM_BG_2( A3_inv_for_NOR4_X4_7T5P0, A3 );

	wire A4_inv_for_NOR4_X4_7T5P0;

	not MGM_BG_3( A4_inv_for_NOR4_X4_7T5P0, A4 );

	and MGM_BG_4( ZN, A1_inv_for_NOR4_X4_7T5P0, A2_inv_for_NOR4_X4_7T5P0, A3_inv_for_NOR4_X4_7T5P0, A4_inv_for_NOR4_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI211_X1_7T5P0_func( A2, ZN, A1, B, C, VDD, VSS );
input A1, A2, B, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI211_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI211_X1_7T5P0, A1 );

	wire A2_inv_for_OAI211_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI211_X1_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI211_X1_7T5P0, A2_inv_for_OAI211_X1_7T5P0 );

	wire B_inv_for_OAI211_X1_7T5P0;

	not MGM_BG_3( B_inv_for_OAI211_X1_7T5P0, B );

	wire C_inv_for_OAI211_X1_7T5P0;

	not MGM_BG_4( C_inv_for_OAI211_X1_7T5P0, C );

	or MGM_BG_5( ZN, ZN_row1, B_inv_for_OAI211_X1_7T5P0, C_inv_for_OAI211_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI211_X2_7T5P0_func( A2, ZN, A1, B, C, VDD, VSS );
input A1, A2, B, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI211_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI211_X2_7T5P0, A1 );

	wire A2_inv_for_OAI211_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI211_X2_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI211_X2_7T5P0, A2_inv_for_OAI211_X2_7T5P0 );

	wire B_inv_for_OAI211_X2_7T5P0;

	not MGM_BG_3( B_inv_for_OAI211_X2_7T5P0, B );

	wire C_inv_for_OAI211_X2_7T5P0;

	not MGM_BG_4( C_inv_for_OAI211_X2_7T5P0, C );

	or MGM_BG_5( ZN, ZN_row1, B_inv_for_OAI211_X2_7T5P0, C_inv_for_OAI211_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI211_X4_7T5P0_func( A2, ZN, A1, B, C, VDD, VSS );
input A1, A2, B, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI211_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI211_X4_7T5P0, A1 );

	wire A2_inv_for_OAI211_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI211_X4_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI211_X4_7T5P0, A2_inv_for_OAI211_X4_7T5P0 );

	wire B_inv_for_OAI211_X4_7T5P0;

	not MGM_BG_3( B_inv_for_OAI211_X4_7T5P0, B );

	wire C_inv_for_OAI211_X4_7T5P0;

	not MGM_BG_4( C_inv_for_OAI211_X4_7T5P0, C );

	or MGM_BG_5( ZN, ZN_row1, B_inv_for_OAI211_X4_7T5P0, C_inv_for_OAI211_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI21_X1_7T5P0_func( A2, ZN, A1, B, VDD, VSS );
input A1, A2, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI21_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI21_X1_7T5P0, A1 );

	wire A2_inv_for_OAI21_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI21_X1_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI21_X1_7T5P0, A2_inv_for_OAI21_X1_7T5P0 );

	wire B_inv_for_OAI21_X1_7T5P0;

	not MGM_BG_3( B_inv_for_OAI21_X1_7T5P0, B );

	or MGM_BG_4( ZN, ZN_row1, B_inv_for_OAI21_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI21_X2_7T5P0_func( B, ZN, A2, A1, VDD, VSS );
input A1, A2, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI21_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI21_X2_7T5P0, A1 );

	wire A2_inv_for_OAI21_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI21_X2_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI21_X2_7T5P0, A2_inv_for_OAI21_X2_7T5P0 );

	wire B_inv_for_OAI21_X2_7T5P0;

	not MGM_BG_3( B_inv_for_OAI21_X2_7T5P0, B );

	or MGM_BG_4( ZN, ZN_row1, B_inv_for_OAI21_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI21_X4_7T5P0_func( A2, ZN, A1, B, VDD, VSS );
input A1, A2, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI21_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI21_X4_7T5P0, A1 );

	wire A2_inv_for_OAI21_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI21_X4_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI21_X4_7T5P0, A2_inv_for_OAI21_X4_7T5P0 );

	wire B_inv_for_OAI21_X4_7T5P0;

	not MGM_BG_3( B_inv_for_OAI21_X4_7T5P0, B );

	or MGM_BG_4( ZN, ZN_row1, B_inv_for_OAI21_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI221_X1_7T5P0_func( B2, B1, C, ZN, A2, A1, VDD, VSS );
input A1, A2, B1, B2, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI221_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI221_X1_7T5P0, A1 );

	wire A2_inv_for_OAI221_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI221_X1_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI221_X1_7T5P0, A2_inv_for_OAI221_X1_7T5P0 );

	wire B1_inv_for_OAI221_X1_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI221_X1_7T5P0, B1 );

	wire B2_inv_for_OAI221_X1_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI221_X1_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI221_X1_7T5P0, B2_inv_for_OAI221_X1_7T5P0 );

	wire C_inv_for_OAI221_X1_7T5P0;

	not MGM_BG_6( C_inv_for_OAI221_X1_7T5P0, C );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2, C_inv_for_OAI221_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI221_X2_7T5P0_func( B2, B1, ZN, C, A1, A2, VDD, VSS );
input A1, A2, B1, B2, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI221_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI221_X2_7T5P0, A1 );

	wire A2_inv_for_OAI221_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI221_X2_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI221_X2_7T5P0, A2_inv_for_OAI221_X2_7T5P0 );

	wire B1_inv_for_OAI221_X2_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI221_X2_7T5P0, B1 );

	wire B2_inv_for_OAI221_X2_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI221_X2_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI221_X2_7T5P0, B2_inv_for_OAI221_X2_7T5P0 );

	wire C_inv_for_OAI221_X2_7T5P0;

	not MGM_BG_6( C_inv_for_OAI221_X2_7T5P0, C );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2, C_inv_for_OAI221_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI221_X4_7T5P0_func( ZN, B1, B2, C, A1, A2, VDD, VSS );
input A1, A2, B1, B2, C;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI221_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI221_X4_7T5P0, A1 );

	wire A2_inv_for_OAI221_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI221_X4_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI221_X4_7T5P0, A2_inv_for_OAI221_X4_7T5P0 );

	wire B1_inv_for_OAI221_X4_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI221_X4_7T5P0, B1 );

	wire B2_inv_for_OAI221_X4_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI221_X4_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI221_X4_7T5P0, B2_inv_for_OAI221_X4_7T5P0 );

	wire C_inv_for_OAI221_X4_7T5P0;

	not MGM_BG_6( C_inv_for_OAI221_X4_7T5P0, C );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2, C_inv_for_OAI221_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI222_X1_7T5P0_func( C2, C1, B1, ZN, B2, A2, A1, VDD, VSS );
input A1, A2, B1, B2, C1, C2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI222_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI222_X1_7T5P0, A1 );

	wire A2_inv_for_OAI222_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI222_X1_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI222_X1_7T5P0, A2_inv_for_OAI222_X1_7T5P0 );

	wire B1_inv_for_OAI222_X1_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI222_X1_7T5P0, B1 );

	wire B2_inv_for_OAI222_X1_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI222_X1_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI222_X1_7T5P0, B2_inv_for_OAI222_X1_7T5P0 );

	wire C1_inv_for_OAI222_X1_7T5P0;

	not MGM_BG_6( C1_inv_for_OAI222_X1_7T5P0, C1 );

	wire C2_inv_for_OAI222_X1_7T5P0;

	not MGM_BG_7( C2_inv_for_OAI222_X1_7T5P0, C2 );

	wire ZN_row3;

	and MGM_BG_8( ZN_row3, C1_inv_for_OAI222_X1_7T5P0, C2_inv_for_OAI222_X1_7T5P0 );

	or MGM_BG_9( ZN, ZN_row1, ZN_row2, ZN_row3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI222_X2_7T5P0_func( ZN, C1, C2, B1, B2, A1, A2, VDD, VSS );
input A1, A2, B1, B2, C1, C2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI222_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI222_X2_7T5P0, A1 );

	wire A2_inv_for_OAI222_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI222_X2_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI222_X2_7T5P0, A2_inv_for_OAI222_X2_7T5P0 );

	wire B1_inv_for_OAI222_X2_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI222_X2_7T5P0, B1 );

	wire B2_inv_for_OAI222_X2_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI222_X2_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI222_X2_7T5P0, B2_inv_for_OAI222_X2_7T5P0 );

	wire C1_inv_for_OAI222_X2_7T5P0;

	not MGM_BG_6( C1_inv_for_OAI222_X2_7T5P0, C1 );

	wire C2_inv_for_OAI222_X2_7T5P0;

	not MGM_BG_7( C2_inv_for_OAI222_X2_7T5P0, C2 );

	wire ZN_row3;

	and MGM_BG_8( ZN_row3, C1_inv_for_OAI222_X2_7T5P0, C2_inv_for_OAI222_X2_7T5P0 );

	or MGM_BG_9( ZN, ZN_row1, ZN_row2, ZN_row3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI222_X4_7T5P0_func( C1, ZN, C2, B1, B2, A1, A2, VDD, VSS );
input A1, A2, B1, B2, C1, C2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI222_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI222_X4_7T5P0, A1 );

	wire A2_inv_for_OAI222_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI222_X4_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI222_X4_7T5P0, A2_inv_for_OAI222_X4_7T5P0 );

	wire B1_inv_for_OAI222_X4_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI222_X4_7T5P0, B1 );

	wire B2_inv_for_OAI222_X4_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI222_X4_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI222_X4_7T5P0, B2_inv_for_OAI222_X4_7T5P0 );

	wire C1_inv_for_OAI222_X4_7T5P0;

	not MGM_BG_6( C1_inv_for_OAI222_X4_7T5P0, C1 );

	wire C2_inv_for_OAI222_X4_7T5P0;

	not MGM_BG_7( C2_inv_for_OAI222_X4_7T5P0, C2 );

	wire ZN_row3;

	and MGM_BG_8( ZN_row3, C1_inv_for_OAI222_X4_7T5P0, C2_inv_for_OAI222_X4_7T5P0 );

	or MGM_BG_9( ZN, ZN_row1, ZN_row2, ZN_row3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI22_X1_7T5P0_func( B2, B1, ZN, A1, A2, VDD, VSS );
input A1, A2, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI22_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI22_X1_7T5P0, A1 );

	wire A2_inv_for_OAI22_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI22_X1_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI22_X1_7T5P0, A2_inv_for_OAI22_X1_7T5P0 );

	wire B1_inv_for_OAI22_X1_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI22_X1_7T5P0, B1 );

	wire B2_inv_for_OAI22_X1_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI22_X1_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI22_X1_7T5P0, B2_inv_for_OAI22_X1_7T5P0 );

	or MGM_BG_6( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI22_X2_7T5P0_func( B2, B1, ZN, A2, A1, VDD, VSS );
input A1, A2, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI22_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI22_X2_7T5P0, A1 );

	wire A2_inv_for_OAI22_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI22_X2_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI22_X2_7T5P0, A2_inv_for_OAI22_X2_7T5P0 );

	wire B1_inv_for_OAI22_X2_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI22_X2_7T5P0, B1 );

	wire B2_inv_for_OAI22_X2_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI22_X2_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI22_X2_7T5P0, B2_inv_for_OAI22_X2_7T5P0 );

	or MGM_BG_6( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI22_X4_7T5P0_func( B2, B1, ZN, A2, A1, VDD, VSS );
input A1, A2, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI22_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI22_X4_7T5P0, A1 );

	wire A2_inv_for_OAI22_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI22_X4_7T5P0, A2 );

	wire ZN_row1;

	and MGM_BG_2( ZN_row1, A1_inv_for_OAI22_X4_7T5P0, A2_inv_for_OAI22_X4_7T5P0 );

	wire B1_inv_for_OAI22_X4_7T5P0;

	not MGM_BG_3( B1_inv_for_OAI22_X4_7T5P0, B1 );

	wire B2_inv_for_OAI22_X4_7T5P0;

	not MGM_BG_4( B2_inv_for_OAI22_X4_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_5( ZN_row2, B1_inv_for_OAI22_X4_7T5P0, B2_inv_for_OAI22_X4_7T5P0 );

	or MGM_BG_6( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI31_X1_7T5P0_func( B, A1, ZN, A2, A3, VDD, VSS );
input A1, A2, A3, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI31_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI31_X1_7T5P0, A1 );

	wire A2_inv_for_OAI31_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI31_X1_7T5P0, A2 );

	wire A3_inv_for_OAI31_X1_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI31_X1_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI31_X1_7T5P0, A2_inv_for_OAI31_X1_7T5P0, A3_inv_for_OAI31_X1_7T5P0 );

	wire B_inv_for_OAI31_X1_7T5P0;

	not MGM_BG_4( B_inv_for_OAI31_X1_7T5P0, B );

	or MGM_BG_5( ZN, ZN_row1, B_inv_for_OAI31_X1_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI31_X2_7T5P0_func( B, ZN, A3, A2, A1, VDD, VSS );
input A1, A2, A3, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI31_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI31_X2_7T5P0, A1 );

	wire A2_inv_for_OAI31_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI31_X2_7T5P0, A2 );

	wire A3_inv_for_OAI31_X2_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI31_X2_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI31_X2_7T5P0, A2_inv_for_OAI31_X2_7T5P0, A3_inv_for_OAI31_X2_7T5P0 );

	wire B_inv_for_OAI31_X2_7T5P0;

	not MGM_BG_4( B_inv_for_OAI31_X2_7T5P0, B );

	or MGM_BG_5( ZN, ZN_row1, B_inv_for_OAI31_X2_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI31_X4_7T5P0_func( A3, ZN, A1, A2, B, VDD, VSS );
input A1, A2, A3, B;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI31_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI31_X4_7T5P0, A1 );

	wire A2_inv_for_OAI31_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI31_X4_7T5P0, A2 );

	wire A3_inv_for_OAI31_X4_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI31_X4_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI31_X4_7T5P0, A2_inv_for_OAI31_X4_7T5P0, A3_inv_for_OAI31_X4_7T5P0 );

	wire B_inv_for_OAI31_X4_7T5P0;

	not MGM_BG_4( B_inv_for_OAI31_X4_7T5P0, B );

	or MGM_BG_5( ZN, ZN_row1, B_inv_for_OAI31_X4_7T5P0 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI32_X1_7T5P0_func( A3, A2, A1, ZN, B1, B2, VDD, VSS );
input A1, A2, A3, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI32_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI32_X1_7T5P0, A1 );

	wire A2_inv_for_OAI32_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI32_X1_7T5P0, A2 );

	wire A3_inv_for_OAI32_X1_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI32_X1_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI32_X1_7T5P0, A2_inv_for_OAI32_X1_7T5P0, A3_inv_for_OAI32_X1_7T5P0 );

	wire B1_inv_for_OAI32_X1_7T5P0;

	not MGM_BG_4( B1_inv_for_OAI32_X1_7T5P0, B1 );

	wire B2_inv_for_OAI32_X1_7T5P0;

	not MGM_BG_5( B2_inv_for_OAI32_X1_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_6( ZN_row2, B1_inv_for_OAI32_X1_7T5P0, B2_inv_for_OAI32_X1_7T5P0 );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI32_X2_7T5P0_func( A3, A2, A1, ZN, B2, B1, VDD, VSS );
input A1, A2, A3, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI32_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI32_X2_7T5P0, A1 );

	wire A2_inv_for_OAI32_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI32_X2_7T5P0, A2 );

	wire A3_inv_for_OAI32_X2_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI32_X2_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI32_X2_7T5P0, A2_inv_for_OAI32_X2_7T5P0, A3_inv_for_OAI32_X2_7T5P0 );

	wire B1_inv_for_OAI32_X2_7T5P0;

	not MGM_BG_4( B1_inv_for_OAI32_X2_7T5P0, B1 );

	wire B2_inv_for_OAI32_X2_7T5P0;

	not MGM_BG_5( B2_inv_for_OAI32_X2_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_6( ZN_row2, B1_inv_for_OAI32_X2_7T5P0, B2_inv_for_OAI32_X2_7T5P0 );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI32_X4_7T5P0_func( A2, A3, A1, ZN, B2, B1, VDD, VSS );
input A1, A2, A3, B1, B2;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI32_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI32_X4_7T5P0, A1 );

	wire A2_inv_for_OAI32_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI32_X4_7T5P0, A2 );

	wire A3_inv_for_OAI32_X4_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI32_X4_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI32_X4_7T5P0, A2_inv_for_OAI32_X4_7T5P0, A3_inv_for_OAI32_X4_7T5P0 );

	wire B1_inv_for_OAI32_X4_7T5P0;

	not MGM_BG_4( B1_inv_for_OAI32_X4_7T5P0, B1 );

	wire B2_inv_for_OAI32_X4_7T5P0;

	not MGM_BG_5( B2_inv_for_OAI32_X4_7T5P0, B2 );

	wire ZN_row2;

	and MGM_BG_6( ZN_row2, B1_inv_for_OAI32_X4_7T5P0, B2_inv_for_OAI32_X4_7T5P0 );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI33_X1_7T5P0_func( B3, B2, B1, ZN, A1, A2, A3, VDD, VSS );
input A1, A2, A3, B1, B2, B3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI33_X1_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI33_X1_7T5P0, A1 );

	wire A2_inv_for_OAI33_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI33_X1_7T5P0, A2 );

	wire A3_inv_for_OAI33_X1_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI33_X1_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI33_X1_7T5P0, A2_inv_for_OAI33_X1_7T5P0, A3_inv_for_OAI33_X1_7T5P0 );

	wire B1_inv_for_OAI33_X1_7T5P0;

	not MGM_BG_4( B1_inv_for_OAI33_X1_7T5P0, B1 );

	wire B2_inv_for_OAI33_X1_7T5P0;

	not MGM_BG_5( B2_inv_for_OAI33_X1_7T5P0, B2 );

	wire B3_inv_for_OAI33_X1_7T5P0;

	not MGM_BG_6( B3_inv_for_OAI33_X1_7T5P0, B3 );

	wire ZN_row2;

	and MGM_BG_7( ZN_row2, B1_inv_for_OAI33_X1_7T5P0, B2_inv_for_OAI33_X1_7T5P0, B3_inv_for_OAI33_X1_7T5P0 );

	or MGM_BG_8( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI33_X2_7T5P0_func( B3, B2, ZN, B1, A3, A2, A1, VDD, VSS );
input A1, A2, A3, B1, B2, B3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI33_X2_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI33_X2_7T5P0, A1 );

	wire A2_inv_for_OAI33_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI33_X2_7T5P0, A2 );

	wire A3_inv_for_OAI33_X2_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI33_X2_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI33_X2_7T5P0, A2_inv_for_OAI33_X2_7T5P0, A3_inv_for_OAI33_X2_7T5P0 );

	wire B1_inv_for_OAI33_X2_7T5P0;

	not MGM_BG_4( B1_inv_for_OAI33_X2_7T5P0, B1 );

	wire B2_inv_for_OAI33_X2_7T5P0;

	not MGM_BG_5( B2_inv_for_OAI33_X2_7T5P0, B2 );

	wire B3_inv_for_OAI33_X2_7T5P0;

	not MGM_BG_6( B3_inv_for_OAI33_X2_7T5P0, B3 );

	wire ZN_row2;

	and MGM_BG_7( ZN_row2, B1_inv_for_OAI33_X2_7T5P0, B2_inv_for_OAI33_X2_7T5P0, B3_inv_for_OAI33_X2_7T5P0 );

	or MGM_BG_8( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OAI33_X4_7T5P0_func( B2, B3, B1, ZN, A1, A2, A3, VDD, VSS );
input A1, A2, A3, B1, B2, B3;
inout VDD, VSS;
output ZN;

	wire A1_inv_for_OAI33_X4_7T5P0;

	not MGM_BG_0( A1_inv_for_OAI33_X4_7T5P0, A1 );

	wire A2_inv_for_OAI33_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_OAI33_X4_7T5P0, A2 );

	wire A3_inv_for_OAI33_X4_7T5P0;

	not MGM_BG_2( A3_inv_for_OAI33_X4_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_3( ZN_row1, A1_inv_for_OAI33_X4_7T5P0, A2_inv_for_OAI33_X4_7T5P0, A3_inv_for_OAI33_X4_7T5P0 );

	wire B1_inv_for_OAI33_X4_7T5P0;

	not MGM_BG_4( B1_inv_for_OAI33_X4_7T5P0, B1 );

	wire B2_inv_for_OAI33_X4_7T5P0;

	not MGM_BG_5( B2_inv_for_OAI33_X4_7T5P0, B2 );

	wire B3_inv_for_OAI33_X4_7T5P0;

	not MGM_BG_6( B3_inv_for_OAI33_X4_7T5P0, B3 );

	wire ZN_row2;

	and MGM_BG_7( ZN_row2, B1_inv_for_OAI33_X4_7T5P0, B2_inv_for_OAI33_X4_7T5P0, B3_inv_for_OAI33_X4_7T5P0 );

	or MGM_BG_8( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR2_X1_7T5P0_func( A1, A2, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR2_X2_7T5P0_func( A1, A2, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR2_X4_7T5P0_func( A2, A1, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR3_X1_7T5P0_func( A1, A2, A3, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2, A3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR3_X2_7T5P0_func( A1, A2, A3, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2, A3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR3_X4_7T5P0_func( A3, A2, A1, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2, A3 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR4_X1_7T5P0_func( A1, A2, A3, A4, Z, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2, A3, A4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR4_X2_7T5P0_func( A1, A2, A3, A4, Z, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2, A3, A4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module OR4_X4_7T5P0_func( A4, A3, A2, A1, Z, VDD, VSS );
input A1, A2, A3, A4;
inout VDD, VSS;
output Z;

	or MGM_BG_0( Z, A1, A2, A3, A4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFQ_X1_7T5P0_func( SE, SI, D, CLK, Q, VDD, VSS, notifier );
input CLK, D, SE, SI, VDD, VSS, notifier;
output Q;

	wire D_inv_for_SDFFQ_X1_7T5P0;

	not MGM_BG_0( D_inv_for_SDFFQ_X1_7T5P0, D );

	wire SE_inv_for_SDFFQ_X1_7T5P0;

	not MGM_BG_1( SE_inv_for_SDFFQ_X1_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_2( MGM_D0_row1, D_inv_for_SDFFQ_X1_7T5P0, SE_inv_for_SDFFQ_X1_7T5P0 );

	wire SI_inv_for_SDFFQ_X1_7T5P0;

	not MGM_BG_3( SI_inv_for_SDFFQ_X1_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_4( MGM_D0_row2, D_inv_for_SDFFQ_X1_7T5P0, SI_inv_for_SDFFQ_X1_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_5( MGM_D0_row3, SI_inv_for_SDFFQ_X1_7T5P0, SE );

	or MGM_BG_6( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_7( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFQ_X2_7T5P0_func( SE, SI, D, CLK, Q, VDD, VSS, notifier );
input CLK, D, SE, SI, VDD, VSS, notifier;
output Q;

	wire D_inv_for_SDFFQ_X2_7T5P0;

	not MGM_BG_0( D_inv_for_SDFFQ_X2_7T5P0, D );

	wire SE_inv_for_SDFFQ_X2_7T5P0;

	not MGM_BG_1( SE_inv_for_SDFFQ_X2_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_2( MGM_D0_row1, D_inv_for_SDFFQ_X2_7T5P0, SE_inv_for_SDFFQ_X2_7T5P0 );

	wire SI_inv_for_SDFFQ_X2_7T5P0;

	not MGM_BG_3( SI_inv_for_SDFFQ_X2_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_4( MGM_D0_row2, D_inv_for_SDFFQ_X2_7T5P0, SI_inv_for_SDFFQ_X2_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_5( MGM_D0_row3, SI_inv_for_SDFFQ_X2_7T5P0, SE );

	or MGM_BG_6( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_7( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFQ_X4_7T5P0_func( SE, SI, D, CLK, Q, VDD, VSS, notifier );
input CLK, D, SE, SI, VDD, VSS, notifier;
output Q;

	wire D_inv_for_SDFFQ_X4_7T5P0;

	not MGM_BG_0( D_inv_for_SDFFQ_X4_7T5P0, D );

	wire SE_inv_for_SDFFQ_X4_7T5P0;

	not MGM_BG_1( SE_inv_for_SDFFQ_X4_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_2( MGM_D0_row1, D_inv_for_SDFFQ_X4_7T5P0, SE_inv_for_SDFFQ_X4_7T5P0 );

	wire SI_inv_for_SDFFQ_X4_7T5P0;

	not MGM_BG_3( SI_inv_for_SDFFQ_X4_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_4( MGM_D0_row2, D_inv_for_SDFFQ_X4_7T5P0, SI_inv_for_SDFFQ_X4_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_5( MGM_D0_row3, SI_inv_for_SDFFQ_X4_7T5P0, SE );

	or MGM_BG_6( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_7( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFRNQ_X1_7T5P0_func( SE, SI, D, CLK, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SE, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	wire D_inv_for_SDFFRNQ_X1_7T5P0;

	not MGM_BG_1( D_inv_for_SDFFRNQ_X1_7T5P0, D );

	wire SE_inv_for_SDFFRNQ_X1_7T5P0;

	not MGM_BG_2( SE_inv_for_SDFFRNQ_X1_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_3( MGM_D0_row1, D_inv_for_SDFFRNQ_X1_7T5P0, SE_inv_for_SDFFRNQ_X1_7T5P0 );

	wire SI_inv_for_SDFFRNQ_X1_7T5P0;

	not MGM_BG_4( SI_inv_for_SDFFRNQ_X1_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_5( MGM_D0_row2, D_inv_for_SDFFRNQ_X1_7T5P0, SI_inv_for_SDFFRNQ_X1_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_6( MGM_D0_row3, SI_inv_for_SDFFRNQ_X1_7T5P0, SE );

	or MGM_BG_7( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_8( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFRNQ_X2_7T5P0_func( SE, SI, D, CLK, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SE, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	wire D_inv_for_SDFFRNQ_X2_7T5P0;

	not MGM_BG_1( D_inv_for_SDFFRNQ_X2_7T5P0, D );

	wire SE_inv_for_SDFFRNQ_X2_7T5P0;

	not MGM_BG_2( SE_inv_for_SDFFRNQ_X2_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_3( MGM_D0_row1, D_inv_for_SDFFRNQ_X2_7T5P0, SE_inv_for_SDFFRNQ_X2_7T5P0 );

	wire SI_inv_for_SDFFRNQ_X2_7T5P0;

	not MGM_BG_4( SI_inv_for_SDFFRNQ_X2_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_5( MGM_D0_row2, D_inv_for_SDFFRNQ_X2_7T5P0, SI_inv_for_SDFFRNQ_X2_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_6( MGM_D0_row3, SI_inv_for_SDFFRNQ_X2_7T5P0, SE );

	or MGM_BG_7( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_8( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFRNQ_X4_7T5P0_func( SE, SI, D, CLK, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SE, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	wire D_inv_for_SDFFRNQ_X4_7T5P0;

	not MGM_BG_1( D_inv_for_SDFFRNQ_X4_7T5P0, D );

	wire SE_inv_for_SDFFRNQ_X4_7T5P0;

	not MGM_BG_2( SE_inv_for_SDFFRNQ_X4_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_3( MGM_D0_row1, D_inv_for_SDFFRNQ_X4_7T5P0, SE_inv_for_SDFFRNQ_X4_7T5P0 );

	wire SI_inv_for_SDFFRNQ_X4_7T5P0;

	not MGM_BG_4( SI_inv_for_SDFFRNQ_X4_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_5( MGM_D0_row2, D_inv_for_SDFFRNQ_X4_7T5P0, SI_inv_for_SDFFRNQ_X4_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_6( MGM_D0_row3, SI_inv_for_SDFFRNQ_X4_7T5P0, SE );

	or MGM_BG_7( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, 1'b0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_8( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFRSNQ_X1_7T5P0_func( SE, SI, D, CLK, SETN, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SE, SETN, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_C0, SETN );

	wire D_inv_for_SDFFRSNQ_X1_7T5P0;

	not MGM_BG_2( D_inv_for_SDFFRSNQ_X1_7T5P0, D );

	wire SE_inv_for_SDFFRSNQ_X1_7T5P0;

	not MGM_BG_3( SE_inv_for_SDFFRSNQ_X1_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_4( MGM_D0_row1, D_inv_for_SDFFRSNQ_X1_7T5P0, SE_inv_for_SDFFRSNQ_X1_7T5P0 );

	wire SI_inv_for_SDFFRSNQ_X1_7T5P0;

	not MGM_BG_5( SI_inv_for_SDFFRSNQ_X1_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_6( MGM_D0_row2, D_inv_for_SDFFRSNQ_X1_7T5P0, SI_inv_for_SDFFRSNQ_X1_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_7( MGM_D0_row3, SI_inv_for_SDFFRSNQ_X1_7T5P0, SE );

	or MGM_BG_8( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_9( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFRSNQ_X2_7T5P0_func( SE, SI, D, CLK, SETN, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SE, SETN, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_C0, SETN );

	wire D_inv_for_SDFFRSNQ_X2_7T5P0;

	not MGM_BG_2( D_inv_for_SDFFRSNQ_X2_7T5P0, D );

	wire SE_inv_for_SDFFRSNQ_X2_7T5P0;

	not MGM_BG_3( SE_inv_for_SDFFRSNQ_X2_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_4( MGM_D0_row1, D_inv_for_SDFFRSNQ_X2_7T5P0, SE_inv_for_SDFFRSNQ_X2_7T5P0 );

	wire SI_inv_for_SDFFRSNQ_X2_7T5P0;

	not MGM_BG_5( SI_inv_for_SDFFRSNQ_X2_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_6( MGM_D0_row2, D_inv_for_SDFFRSNQ_X2_7T5P0, SI_inv_for_SDFFRSNQ_X2_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_7( MGM_D0_row3, SI_inv_for_SDFFRSNQ_X2_7T5P0, SE );

	or MGM_BG_8( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_9( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFRSNQ_X4_7T5P0_func( SE, SI, D, CLK, SETN, RN, Q, VDD, VSS, notifier );
input CLK, D, RN, SE, SETN, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_P0, RN );

	not MGM_BG_1( MGM_C0, SETN );

	wire D_inv_for_SDFFRSNQ_X4_7T5P0;

	not MGM_BG_2( D_inv_for_SDFFRSNQ_X4_7T5P0, D );

	wire SE_inv_for_SDFFRSNQ_X4_7T5P0;

	not MGM_BG_3( SE_inv_for_SDFFRSNQ_X4_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_4( MGM_D0_row1, D_inv_for_SDFFRSNQ_X4_7T5P0, SE_inv_for_SDFFRSNQ_X4_7T5P0 );

	wire SI_inv_for_SDFFRSNQ_X4_7T5P0;

	not MGM_BG_5( SI_inv_for_SDFFRSNQ_X4_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_6( MGM_D0_row2, D_inv_for_SDFFRSNQ_X4_7T5P0, SI_inv_for_SDFFRSNQ_X4_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_7( MGM_D0_row3, SI_inv_for_SDFFRSNQ_X4_7T5P0, SE );

	or MGM_BG_8( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_HN_IQ_FF_UDP( IQ1, MGM_C0, MGM_P0, CLK, MGM_D0, notifier );

	not MGM_BG_9( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFSNQ_X1_7T5P0_func( SE, SI, D, CLK, SETN, Q, VDD, VSS, notifier );
input CLK, D, SE, SETN, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, SETN );

	wire D_inv_for_SDFFSNQ_X1_7T5P0;

	not MGM_BG_1( D_inv_for_SDFFSNQ_X1_7T5P0, D );

	wire SE_inv_for_SDFFSNQ_X1_7T5P0;

	not MGM_BG_2( SE_inv_for_SDFFSNQ_X1_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_3( MGM_D0_row1, D_inv_for_SDFFSNQ_X1_7T5P0, SE_inv_for_SDFFSNQ_X1_7T5P0 );

	wire SI_inv_for_SDFFSNQ_X1_7T5P0;

	not MGM_BG_4( SI_inv_for_SDFFSNQ_X1_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_5( MGM_D0_row2, D_inv_for_SDFFSNQ_X1_7T5P0, SI_inv_for_SDFFSNQ_X1_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_6( MGM_D0_row3, SI_inv_for_SDFFSNQ_X1_7T5P0, SE );

	or MGM_BG_7( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_8( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFSNQ_X2_7T5P0_func( SE, SI, D, CLK, SETN, Q, VDD, VSS, notifier );
input CLK, D, SE, SETN, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, SETN );

	wire D_inv_for_SDFFSNQ_X2_7T5P0;

	not MGM_BG_1( D_inv_for_SDFFSNQ_X2_7T5P0, D );

	wire SE_inv_for_SDFFSNQ_X2_7T5P0;

	not MGM_BG_2( SE_inv_for_SDFFSNQ_X2_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_3( MGM_D0_row1, D_inv_for_SDFFSNQ_X2_7T5P0, SE_inv_for_SDFFSNQ_X2_7T5P0 );

	wire SI_inv_for_SDFFSNQ_X2_7T5P0;

	not MGM_BG_4( SI_inv_for_SDFFSNQ_X2_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_5( MGM_D0_row2, D_inv_for_SDFFSNQ_X2_7T5P0, SI_inv_for_SDFFSNQ_X2_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_6( MGM_D0_row3, SI_inv_for_SDFFSNQ_X2_7T5P0, SE );

	or MGM_BG_7( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_8( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module SDFFSNQ_X4_7T5P0_func( SE, SI, D, CLK, SETN, Q, VDD, VSS, notifier );
input CLK, D, SE, SETN, SI, VDD, VSS, notifier;
output Q;

	not MGM_BG_0( MGM_C0, SETN );

	wire D_inv_for_SDFFSNQ_X4_7T5P0;

	not MGM_BG_1( D_inv_for_SDFFSNQ_X4_7T5P0, D );

	wire SE_inv_for_SDFFSNQ_X4_7T5P0;

	not MGM_BG_2( SE_inv_for_SDFFSNQ_X4_7T5P0, SE );

	wire MGM_D0_row1;

	and MGM_BG_3( MGM_D0_row1, D_inv_for_SDFFSNQ_X4_7T5P0, SE_inv_for_SDFFSNQ_X4_7T5P0 );

	wire SI_inv_for_SDFFSNQ_X4_7T5P0;

	not MGM_BG_4( SI_inv_for_SDFFSNQ_X4_7T5P0, SI );

	wire MGM_D0_row2;

	and MGM_BG_5( MGM_D0_row2, D_inv_for_SDFFSNQ_X4_7T5P0, SI_inv_for_SDFFSNQ_X4_7T5P0 );

	wire MGM_D0_row3;

	and MGM_BG_6( MGM_D0_row3, SI_inv_for_SDFFSNQ_X4_7T5P0, SE );

	or MGM_BG_7( MGM_D0, MGM_D0_row1, MGM_D0_row2, MGM_D0_row3 );

	UDP_GF018hv5v_mcu_sc7_TT_5P0V_25C_verilog_pg_MGM_N_IQ_FF_UDP( IQ1, MGM_C0, 1'b0, CLK, MGM_D0, notifier );

	not MGM_BG_8( Q, IQ1 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module TIEH_7T5P0_func( Z, VDD, VSS );
inout VDD, VSS;
output Z;

	assign Z = 1'b1;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module TIEL_7T5P0_func( ZN, VDD, VSS );
inout VDD, VSS;
output ZN;

	assign ZN = 1'b0;

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XNOR2_X1_7T5P0_func( A2, A1, ZN, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire ZN_row1;

	and MGM_BG_0( ZN_row1, A1, A2 );

	wire A1_inv_for_XNOR2_X1_7T5P0;

	not MGM_BG_1( A1_inv_for_XNOR2_X1_7T5P0, A1 );

	wire A2_inv_for_XNOR2_X1_7T5P0;

	not MGM_BG_2( A2_inv_for_XNOR2_X1_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_3( ZN_row2, A1_inv_for_XNOR2_X1_7T5P0, A2_inv_for_XNOR2_X1_7T5P0 );

	or MGM_BG_4( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XNOR2_X2_7T5P0_func( A2, A1, ZN, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire ZN_row1;

	and MGM_BG_0( ZN_row1, A1, A2 );

	wire A1_inv_for_XNOR2_X2_7T5P0;

	not MGM_BG_1( A1_inv_for_XNOR2_X2_7T5P0, A1 );

	wire A2_inv_for_XNOR2_X2_7T5P0;

	not MGM_BG_2( A2_inv_for_XNOR2_X2_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_3( ZN_row2, A1_inv_for_XNOR2_X2_7T5P0, A2_inv_for_XNOR2_X2_7T5P0 );

	or MGM_BG_4( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XNOR2_X4_7T5P0_func( A2, A1, ZN, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output ZN;

	wire ZN_row1;

	and MGM_BG_0( ZN_row1, A1, A2 );

	wire A1_inv_for_XNOR2_X4_7T5P0;

	not MGM_BG_1( A1_inv_for_XNOR2_X4_7T5P0, A1 );

	wire A2_inv_for_XNOR2_X4_7T5P0;

	not MGM_BG_2( A2_inv_for_XNOR2_X4_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_3( ZN_row2, A1_inv_for_XNOR2_X4_7T5P0, A2_inv_for_XNOR2_X4_7T5P0 );

	or MGM_BG_4( ZN, ZN_row1, ZN_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XNOR3_X1_7T5P0_func( A2, A1, A3, ZN, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A3_inv_for_XNOR3_X1_7T5P0;

	not MGM_BG_0( A3_inv_for_XNOR3_X1_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_1( ZN_row1, A3_inv_for_XNOR3_X1_7T5P0, A1, A2 );

	wire A2_inv_for_XNOR3_X1_7T5P0;

	not MGM_BG_2( A2_inv_for_XNOR3_X1_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_3( ZN_row2, A2_inv_for_XNOR3_X1_7T5P0, A1, A3 );

	wire A1_inv_for_XNOR3_X1_7T5P0;

	not MGM_BG_4( A1_inv_for_XNOR3_X1_7T5P0, A1 );

	wire ZN_row3;

	and MGM_BG_5( ZN_row3, A1_inv_for_XNOR3_X1_7T5P0, A2, A3 );

	wire ZN_row4;

	and MGM_BG_6( ZN_row4, A1_inv_for_XNOR3_X1_7T5P0, A2_inv_for_XNOR3_X1_7T5P0, A3_inv_for_XNOR3_X1_7T5P0 );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XNOR3_X2_7T5P0_func( A2, A1, A3, ZN, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A3_inv_for_XNOR3_X2_7T5P0;

	not MGM_BG_0( A3_inv_for_XNOR3_X2_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_1( ZN_row1, A3_inv_for_XNOR3_X2_7T5P0, A1, A2 );

	wire A2_inv_for_XNOR3_X2_7T5P0;

	not MGM_BG_2( A2_inv_for_XNOR3_X2_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_3( ZN_row2, A2_inv_for_XNOR3_X2_7T5P0, A1, A3 );

	wire A1_inv_for_XNOR3_X2_7T5P0;

	not MGM_BG_4( A1_inv_for_XNOR3_X2_7T5P0, A1 );

	wire ZN_row3;

	and MGM_BG_5( ZN_row3, A1_inv_for_XNOR3_X2_7T5P0, A2, A3 );

	wire ZN_row4;

	and MGM_BG_6( ZN_row4, A1_inv_for_XNOR3_X2_7T5P0, A2_inv_for_XNOR3_X2_7T5P0, A3_inv_for_XNOR3_X2_7T5P0 );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XNOR3_X4_7T5P0_func( A2, A1, A3, ZN, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output ZN;

	wire A3_inv_for_XNOR3_X4_7T5P0;

	not MGM_BG_0( A3_inv_for_XNOR3_X4_7T5P0, A3 );

	wire ZN_row1;

	and MGM_BG_1( ZN_row1, A3_inv_for_XNOR3_X4_7T5P0, A1, A2 );

	wire A2_inv_for_XNOR3_X4_7T5P0;

	not MGM_BG_2( A2_inv_for_XNOR3_X4_7T5P0, A2 );

	wire ZN_row2;

	and MGM_BG_3( ZN_row2, A2_inv_for_XNOR3_X4_7T5P0, A1, A3 );

	wire A1_inv_for_XNOR3_X4_7T5P0;

	not MGM_BG_4( A1_inv_for_XNOR3_X4_7T5P0, A1 );

	wire ZN_row3;

	and MGM_BG_5( ZN_row3, A1_inv_for_XNOR3_X4_7T5P0, A2, A3 );

	wire ZN_row4;

	and MGM_BG_6( ZN_row4, A1_inv_for_XNOR3_X4_7T5P0, A2_inv_for_XNOR3_X4_7T5P0, A3_inv_for_XNOR3_X4_7T5P0 );

	or MGM_BG_7( ZN, ZN_row1, ZN_row2, ZN_row3, ZN_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XOR2_X1_7T5P0_func( A2, A1, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	wire A2_inv_for_XOR2_X1_7T5P0;

	not MGM_BG_0( A2_inv_for_XOR2_X1_7T5P0, A2 );

	wire Z_row1;

	and MGM_BG_1( Z_row1, A2_inv_for_XOR2_X1_7T5P0, A1 );

	wire A1_inv_for_XOR2_X1_7T5P0;

	not MGM_BG_2( A1_inv_for_XOR2_X1_7T5P0, A1 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, A1_inv_for_XOR2_X1_7T5P0, A2 );

	or MGM_BG_4( Z, Z_row1, Z_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XOR2_X2_7T5P0_func( A2, A1, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	wire A2_inv_for_XOR2_X2_7T5P0;

	not MGM_BG_0( A2_inv_for_XOR2_X2_7T5P0, A2 );

	wire Z_row1;

	and MGM_BG_1( Z_row1, A2_inv_for_XOR2_X2_7T5P0, A1 );

	wire A1_inv_for_XOR2_X2_7T5P0;

	not MGM_BG_2( A1_inv_for_XOR2_X2_7T5P0, A1 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, A1_inv_for_XOR2_X2_7T5P0, A2 );

	or MGM_BG_4( Z, Z_row1, Z_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XOR2_X4_7T5P0_func( A2, A1, Z, VDD, VSS );
input A1, A2;
inout VDD, VSS;
output Z;

	wire A2_inv_for_XOR2_X4_7T5P0;

	not MGM_BG_0( A2_inv_for_XOR2_X4_7T5P0, A2 );

	wire Z_row1;

	and MGM_BG_1( Z_row1, A2_inv_for_XOR2_X4_7T5P0, A1 );

	wire A1_inv_for_XOR2_X4_7T5P0;

	not MGM_BG_2( A1_inv_for_XOR2_X4_7T5P0, A1 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, A1_inv_for_XOR2_X4_7T5P0, A2 );

	or MGM_BG_4( Z, Z_row1, Z_row2 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XOR3_X1_7T5P0_func( A2, A1, A3, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	wire Z_row1;

	and MGM_BG_0( Z_row1, A1, A2, A3 );

	wire A2_inv_for_XOR3_X1_7T5P0;

	not MGM_BG_1( A2_inv_for_XOR3_X1_7T5P0, A2 );

	wire A3_inv_for_XOR3_X1_7T5P0;

	not MGM_BG_2( A3_inv_for_XOR3_X1_7T5P0, A3 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, A2_inv_for_XOR3_X1_7T5P0, A3_inv_for_XOR3_X1_7T5P0, A1 );

	wire A1_inv_for_XOR3_X1_7T5P0;

	not MGM_BG_4( A1_inv_for_XOR3_X1_7T5P0, A1 );

	wire Z_row3;

	and MGM_BG_5( Z_row3, A1_inv_for_XOR3_X1_7T5P0, A3_inv_for_XOR3_X1_7T5P0, A2 );

	wire Z_row4;

	and MGM_BG_6( Z_row4, A1_inv_for_XOR3_X1_7T5P0, A2_inv_for_XOR3_X1_7T5P0, A3 );

	or MGM_BG_7( Z, Z_row1, Z_row2, Z_row3, Z_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XOR3_X2_7T5P0_func( A2, A1, A3, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	wire Z_row1;

	and MGM_BG_0( Z_row1, A1, A2, A3 );

	wire A2_inv_for_XOR3_X2_7T5P0;

	not MGM_BG_1( A2_inv_for_XOR3_X2_7T5P0, A2 );

	wire A3_inv_for_XOR3_X2_7T5P0;

	not MGM_BG_2( A3_inv_for_XOR3_X2_7T5P0, A3 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, A2_inv_for_XOR3_X2_7T5P0, A3_inv_for_XOR3_X2_7T5P0, A1 );

	wire A1_inv_for_XOR3_X2_7T5P0;

	not MGM_BG_4( A1_inv_for_XOR3_X2_7T5P0, A1 );

	wire Z_row3;

	and MGM_BG_5( Z_row3, A1_inv_for_XOR3_X2_7T5P0, A3_inv_for_XOR3_X2_7T5P0, A2 );

	wire Z_row4;

	and MGM_BG_6( Z_row4, A1_inv_for_XOR3_X2_7T5P0, A2_inv_for_XOR3_X2_7T5P0, A3 );

	or MGM_BG_7( Z, Z_row1, Z_row2, Z_row3, Z_row4 );

endmodule
`endcelldefine
// udp_data_end
// udp_data_begin


`celldefine
module XOR3_X4_7T5P0_func( A2, A1, A3, Z, VDD, VSS );
input A1, A2, A3;
inout VDD, VSS;
output Z;

	wire Z_row1;

	and MGM_BG_0( Z_row1, A1, A2, A3 );

	wire A2_inv_for_XOR3_X4_7T5P0;

	not MGM_BG_1( A2_inv_for_XOR3_X4_7T5P0, A2 );

	wire A3_inv_for_XOR3_X4_7T5P0;

	not MGM_BG_2( A3_inv_for_XOR3_X4_7T5P0, A3 );

	wire Z_row2;

	and MGM_BG_3( Z_row2, A2_inv_for_XOR3_X4_7T5P0, A3_inv_for_XOR3_X4_7T5P0, A1 );

	wire A1_inv_for_XOR3_X4_7T5P0;

	not MGM_BG_4( A1_inv_for_XOR3_X4_7T5P0, A1 );

	wire Z_row3;

	and MGM_BG_5( Z_row3, A1_inv_for_XOR3_X4_7T5P0, A3_inv_for_XOR3_X4_7T5P0, A2 );

	wire Z_row4;

	and MGM_BG_6( Z_row4, A1_inv_for_XOR3_X4_7T5P0, A2_inv_for_XOR3_X4_7T5P0, A3 );

	or MGM_BG_7( Z, Z_row1, Z_row2, Z_row3, Z_row4 );

endmodule
`endcelldefine
// udp_data_end