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foss-eda-tools / gf180mcu-private / 94f72663a948325f21395b5f16bba0aaebb8bc3f / . / GF018hv5v_green_sc9_2016q2v1 / verilog / GF018hv5v_green_sc9_nonpg.v
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//****************************************************************************//
// //
/* Revision: 1.2 */
// File generated on Thu May 19 13:36:48 PDT 2016. ( GF ) //
//****************************************************************************//
`timescale 1ns/1ps
`celldefine
module ADDF_X1( S, A, CI, B, CO );
input A, B, CI;
output CO, S;
`ifdef FUNCTIONAL // functional //
ADDF_X1_func ADDF_X1_behav_inst(.S(S),.A(A),.CI(CI),.B(B),.CO(CO));
`else
ADDF_X1_func ADDF_X1_inst(.S(S),.A(A),.CI(CI),.B(B),.CO(CO));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B===1'b0 && CI===1'b1)
// comb arc A --> CO
(A => CO) = (1.0,1.0);
if(B===1'b1 && CI===1'b0)
// comb arc A --> CO
(A => CO) = (1.0,1.0);
ifnone
// comb arc A --> CO
(A => CO) = (1.0,1.0);
if(A===1'b0 && CI===1'b1)
// comb arc B --> CO
(B => CO) = (1.0,1.0);
if(A===1'b1 && CI===1'b0)
// comb arc B --> CO
(B => CO) = (1.0,1.0);
ifnone
// comb arc B --> CO
(B => CO) = (1.0,1.0);
if(A===1'b0 && B===1'b1)
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
if(A===1'b1 && B===1'b0)
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
ifnone
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
if(B===1'b0 && CI===1'b1)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(B===1'b1 && CI===1'b0)
// comb arc A --> S
(A => S) = (1.0,1.0);
ifnone
// comb arc posedge A --> (S:A)
(posedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc negedge A --> (S:A)
(negedge A => (S:A)) = (1.0,1.0);
if(B===1'b0 && CI===1'b0)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(B===1'b1 && CI===1'b1)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(A===1'b0 && CI===1'b1)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b1 && CI===1'b0)
// comb arc B --> S
(B => S) = (1.0,1.0);
ifnone
// comb arc posedge B --> (S:B)
(posedge B => (S:B)) = (1.0,1.0);
ifnone
// comb arc negedge B --> (S:B)
(negedge B => (S:B)) = (1.0,1.0);
if(A===1'b0 && CI===1'b0)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b1 && CI===1'b1)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b0 && B===1'b1)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
if(A===1'b1 && B===1'b0)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
ifnone
// comb arc posedge CI --> (S:CI)
(posedge CI => (S:CI)) = (1.0,1.0);
ifnone
// comb arc negedge CI --> (S:CI)
(negedge CI => (S:CI)) = (1.0,1.0);
if(A===1'b0 && B===1'b0)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
if(A===1'b1 && B===1'b1)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ADDF_X2( S, A, CI, B, CO );
input A, B, CI;
output CO, S;
`ifdef FUNCTIONAL // functional //
ADDF_X2_func ADDF_X2_behav_inst(.S(S),.A(A),.CI(CI),.B(B),.CO(CO));
`else
ADDF_X2_func ADDF_X2_inst(.S(S),.A(A),.CI(CI),.B(B),.CO(CO));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B===1'b0 && CI===1'b1)
// comb arc A --> CO
(A => CO) = (1.0,1.0);
if(B===1'b1 && CI===1'b0)
// comb arc A --> CO
(A => CO) = (1.0,1.0);
ifnone
// comb arc A --> CO
(A => CO) = (1.0,1.0);
if(A===1'b0 && CI===1'b1)
// comb arc B --> CO
(B => CO) = (1.0,1.0);
if(A===1'b1 && CI===1'b0)
// comb arc B --> CO
(B => CO) = (1.0,1.0);
ifnone
// comb arc B --> CO
(B => CO) = (1.0,1.0);
if(A===1'b0 && B===1'b1)
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
if(A===1'b1 && B===1'b0)
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
ifnone
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
if(B===1'b0 && CI===1'b1)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(B===1'b1 && CI===1'b0)
// comb arc A --> S
(A => S) = (1.0,1.0);
ifnone
// comb arc posedge A --> (S:A)
(posedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc negedge A --> (S:A)
(negedge A => (S:A)) = (1.0,1.0);
if(B===1'b0 && CI===1'b0)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(B===1'b1 && CI===1'b1)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(A===1'b0 && CI===1'b1)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b1 && CI===1'b0)
// comb arc B --> S
(B => S) = (1.0,1.0);
ifnone
// comb arc posedge B --> (S:B)
(posedge B => (S:B)) = (1.0,1.0);
ifnone
// comb arc negedge B --> (S:B)
(negedge B => (S:B)) = (1.0,1.0);
if(A===1'b0 && CI===1'b0)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b1 && CI===1'b1)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b0 && B===1'b1)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
if(A===1'b1 && B===1'b0)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
ifnone
// comb arc posedge CI --> (S:CI)
(posedge CI => (S:CI)) = (1.0,1.0);
ifnone
// comb arc negedge CI --> (S:CI)
(negedge CI => (S:CI)) = (1.0,1.0);
if(A===1'b0 && B===1'b0)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
if(A===1'b1 && B===1'b1)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ADDF_X4( S, A, CI, B, CO );
input A, B, CI;
output CO, S;
`ifdef FUNCTIONAL // functional //
ADDF_X4_func ADDF_X4_behav_inst(.S(S),.A(A),.CI(CI),.B(B),.CO(CO));
`else
ADDF_X4_func ADDF_X4_inst(.S(S),.A(A),.CI(CI),.B(B),.CO(CO));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B===1'b0 && CI===1'b1)
// comb arc A --> CO
(A => CO) = (1.0,1.0);
if(B===1'b1 && CI===1'b0)
// comb arc A --> CO
(A => CO) = (1.0,1.0);
ifnone
// comb arc A --> CO
(A => CO) = (1.0,1.0);
if(A===1'b0 && CI===1'b1)
// comb arc B --> CO
(B => CO) = (1.0,1.0);
if(A===1'b1 && CI===1'b0)
// comb arc B --> CO
(B => CO) = (1.0,1.0);
ifnone
// comb arc B --> CO
(B => CO) = (1.0,1.0);
if(A===1'b0 && B===1'b1)
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
if(A===1'b1 && B===1'b0)
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
ifnone
// comb arc CI --> CO
(CI => CO) = (1.0,1.0);
if(B===1'b0 && CI===1'b1)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(B===1'b1 && CI===1'b0)
// comb arc A --> S
(A => S) = (1.0,1.0);
ifnone
// comb arc posedge A --> (S:A)
(posedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc negedge A --> (S:A)
(negedge A => (S:A)) = (1.0,1.0);
if(B===1'b0 && CI===1'b0)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(B===1'b1 && CI===1'b1)
// comb arc A --> S
(A => S) = (1.0,1.0);
if(A===1'b0 && CI===1'b1)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b1 && CI===1'b0)
// comb arc B --> S
(B => S) = (1.0,1.0);
ifnone
// comb arc posedge B --> (S:B)
(posedge B => (S:B)) = (1.0,1.0);
ifnone
// comb arc negedge B --> (S:B)
(negedge B => (S:B)) = (1.0,1.0);
if(A===1'b0 && CI===1'b0)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b1 && CI===1'b1)
// comb arc B --> S
(B => S) = (1.0,1.0);
if(A===1'b0 && B===1'b1)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
if(A===1'b1 && B===1'b0)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
ifnone
// comb arc posedge CI --> (S:CI)
(posedge CI => (S:CI)) = (1.0,1.0);
ifnone
// comb arc negedge CI --> (S:CI)
(negedge CI => (S:CI)) = (1.0,1.0);
if(A===1'b0 && B===1'b0)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
if(A===1'b1 && B===1'b1)
// comb arc CI --> S
(CI => S) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ADDH_X1( CO, A, B, S );
input A, B;
output CO, S;
`ifdef FUNCTIONAL // functional //
ADDH_X1_func ADDH_X1_behav_inst(.CO(CO),.A(A),.B(B),.S(S));
`else
ADDH_X1_func ADDH_X1_inst(.CO(CO),.A(A),.B(B),.S(S));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A --> CO
(A => CO) = (1.0,1.0);
// comb arc B --> CO
(B => CO) = (1.0,1.0);
ifnone
// comb arc posedge A --> (S:A)
(posedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc negedge A --> (S:A)
(negedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc posedge B --> (S:B)
(posedge B => (S:B)) = (1.0,1.0);
ifnone
// comb arc negedge B --> (S:B)
(negedge B => (S:B)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ADDH_X2( CO, A, B, S );
input A, B;
output CO, S;
`ifdef FUNCTIONAL // functional //
ADDH_X2_func ADDH_X2_behav_inst(.CO(CO),.A(A),.B(B),.S(S));
`else
ADDH_X2_func ADDH_X2_inst(.CO(CO),.A(A),.B(B),.S(S));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A --> CO
(A => CO) = (1.0,1.0);
// comb arc B --> CO
(B => CO) = (1.0,1.0);
ifnone
// comb arc posedge A --> (S:A)
(posedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc negedge A --> (S:A)
(negedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc posedge B --> (S:B)
(posedge B => (S:B)) = (1.0,1.0);
ifnone
// comb arc negedge B --> (S:B)
(negedge B => (S:B)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ADDH_X4( A, B, CO, S );
input A, B;
output CO, S;
`ifdef FUNCTIONAL // functional //
ADDH_X4_func ADDH_X4_behav_inst(.A(A),.B(B),.CO(CO),.S(S));
`else
ADDH_X4_func ADDH_X4_inst(.A(A),.B(B),.CO(CO),.S(S));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A --> CO
(A => CO) = (1.0,1.0);
// comb arc B --> CO
(B => CO) = (1.0,1.0);
ifnone
// comb arc posedge A --> (S:A)
(posedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc negedge A --> (S:A)
(negedge A => (S:A)) = (1.0,1.0);
ifnone
// comb arc posedge B --> (S:B)
(posedge B => (S:B)) = (1.0,1.0);
ifnone
// comb arc negedge B --> (S:B)
(negedge B => (S:B)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND2_X1( A1, A2, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
AND2_X1_func AND2_X1_behav_inst(.A1(A1),.A2(A2),.Z(Z));
`else
AND2_X1_func AND2_X1_inst(.A1(A1),.A2(A2),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND2_X2( A1, A2, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
AND2_X2_func AND2_X2_behav_inst(.A1(A1),.A2(A2),.Z(Z));
`else
AND2_X2_func AND2_X2_inst(.A1(A1),.A2(A2),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND2_X4( A2, A1, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
AND2_X4_func AND2_X4_behav_inst(.A2(A2),.A1(A1),.Z(Z));
`else
AND2_X4_func AND2_X4_inst(.A2(A2),.A1(A1),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND3_X1( A1, A3, A2, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
AND3_X1_func AND3_X1_behav_inst(.A1(A1),.A3(A3),.A2(A2),.Z(Z));
`else
AND3_X1_func AND3_X1_inst(.A1(A1),.A3(A3),.A2(A2),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND3_X2( A1, A2, A3, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
AND3_X2_func AND3_X2_behav_inst(.A1(A1),.A2(A2),.A3(A3),.Z(Z));
`else
AND3_X2_func AND3_X2_inst(.A1(A1),.A2(A2),.A3(A3),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND3_X4( A3, A1, A2, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
AND3_X4_func AND3_X4_behav_inst(.A3(A3),.A1(A1),.A2(A2),.Z(Z));
`else
AND3_X4_func AND3_X4_inst(.A3(A3),.A1(A1),.A2(A2),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND4_X1( A1, A2, A3, A4, Z );
input A1, A2, A3, A4;
output Z;
`ifdef FUNCTIONAL // functional //
AND4_X1_func AND4_X1_behav_inst(.A1(A1),.A2(A2),.A3(A3),.A4(A4),.Z(Z));
`else
AND4_X1_func AND4_X1_inst(.A1(A1),.A2(A2),.A3(A3),.A4(A4),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// comb arc A4 --> Z
(A4 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND4_X2( A1, A2, A3, A4, Z );
input A1, A2, A3, A4;
output Z;
`ifdef FUNCTIONAL // functional //
AND4_X2_func AND4_X2_behav_inst(.A1(A1),.A2(A2),.A3(A3),.A4(A4),.Z(Z));
`else
AND4_X2_func AND4_X2_inst(.A1(A1),.A2(A2),.A3(A3),.A4(A4),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// comb arc A4 --> Z
(A4 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AND4_X4( A4, A3, A1, A2, Z );
input A1, A2, A3, A4;
output Z;
`ifdef FUNCTIONAL // functional //
AND4_X4_func AND4_X4_behav_inst(.A4(A4),.A3(A3),.A1(A1),.A2(A2),.Z(Z));
`else
AND4_X4_func AND4_X4_inst(.A4(A4),.A3(A3),.A1(A1),.A2(A2),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// comb arc A4 --> Z
(A4 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ANTENNA( I );
input I;
`ifdef FUNCTIONAL // functional //
ANTENNA_func ANTENNA_behav_inst(.I(I));
`else
ANTENNA_func ANTENNA_inst(.I(I));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI211_X1( A2, ZN, A1, B, C );
input A1, A2, B, C;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI211_X1_func AOI211_X1_behav_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B),.C(C));
`else
AOI211_X1_func AOI211_X1_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B),.C(C));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI211_X2( A2, ZN, A1, B, C );
input A1, A2, B, C;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI211_X2_func AOI211_X2_behav_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B),.C(C));
`else
AOI211_X2_func AOI211_X2_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B),.C(C));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI211_X4( ZN, A2, A1, B, C );
input A1, A2, B, C;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI211_X4_func AOI211_X4_behav_inst(.ZN(ZN),.A2(A2),.A1(A1),.B(B),.C(C));
`else
AOI211_X4_func AOI211_X4_inst(.ZN(ZN),.A2(A2),.A1(A1),.B(B),.C(C));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI21_X1( A2, ZN, A1, B );
input A1, A2, B;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI21_X1_func AOI21_X1_behav_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B));
`else
AOI21_X1_func AOI21_X1_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI21_X2( B, ZN, A2, A1 );
input A1, A2, B;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI21_X2_func AOI21_X2_behav_inst(.B(B),.ZN(ZN),.A2(A2),.A1(A1));
`else
AOI21_X2_func AOI21_X2_inst(.B(B),.ZN(ZN),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI21_X4( A1, A2, ZN, B );
input A1, A2, B;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI21_X4_func AOI21_X4_behav_inst(.A1(A1),.A2(A2),.ZN(ZN),.B(B));
`else
AOI21_X4_func AOI21_X4_inst(.A1(A1),.A2(A2),.ZN(ZN),.B(B));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI221_X1( B2, B1, C, ZN, A2, A1 );
input A1, A2, B1, B2, C;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI221_X1_func AOI221_X1_behav_inst(.B2(B2),.B1(B1),.C(C),.ZN(ZN),.A2(A2),.A1(A1));
`else
AOI221_X1_func AOI221_X1_inst(.B2(B2),.B1(B1),.C(C),.ZN(ZN),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI221_X2( ZN, C, B2, B1, A1, A2 );
input A1, A2, B1, B2, C;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI221_X2_func AOI221_X2_behav_inst(.ZN(ZN),.C(C),.B2(B2),.B1(B1),.A1(A1),.A2(A2));
`else
AOI221_X2_func AOI221_X2_inst(.ZN(ZN),.C(C),.B2(B2),.B1(B1),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI221_X4( ZN, B1, B2, C, A1, A2 );
input A1, A2, B1, B2, C;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI221_X4_func AOI221_X4_behav_inst(.ZN(ZN),.B1(B1),.B2(B2),.C(C),.A1(A1),.A2(A2));
`else
AOI221_X4_func AOI221_X4_inst(.ZN(ZN),.B1(B1),.B2(B2),.C(C),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI222_X1( C2, C1, B1, ZN, B2, A2, A1 );
input A1, A2, B1, B2, C1, C2;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI222_X1_func AOI222_X1_behav_inst(.C2(C2),.C1(C1),.B1(B1),.ZN(ZN),.B2(B2),.A2(A2),.A1(A1));
`else
AOI222_X1_func AOI222_X1_inst(.C2(C2),.C1(C1),.B1(B1),.ZN(ZN),.B2(B2),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
ifnone
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
ifnone
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI222_X2( C1, ZN, C2, B2, B1, A1, A2 );
input A1, A2, B1, B2, C1, C2;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI222_X2_func AOI222_X2_behav_inst(.C1(C1),.ZN(ZN),.C2(C2),.B2(B2),.B1(B1),.A1(A1),.A2(A2));
`else
AOI222_X2_func AOI222_X2_inst(.C1(C1),.ZN(ZN),.C2(C2),.B2(B2),.B1(B1),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
ifnone
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
ifnone
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI222_X4( ZN, C1, C2, B1, B2, A1, A2 );
input A1, A2, B1, B2, C1, C2;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI222_X4_func AOI222_X4_behav_inst(.ZN(ZN),.C1(C1),.C2(C2),.B1(B1),.B2(B2),.A1(A1),.A2(A2));
`else
AOI222_X4_func AOI222_X4_inst(.ZN(ZN),.C1(C1),.C2(C2),.B1(B1),.B2(B2),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
ifnone
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
ifnone
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI22_X1( B2, B1, ZN, A1, A2 );
input A1, A2, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI22_X1_func AOI22_X1_behav_inst(.B2(B2),.B1(B1),.ZN(ZN),.A1(A1),.A2(A2));
`else
AOI22_X1_func AOI22_X1_inst(.B2(B2),.B1(B1),.ZN(ZN),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI22_X2( B2, B1, ZN, A2, A1 );
input A1, A2, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI22_X2_func AOI22_X2_behav_inst(.B2(B2),.B1(B1),.ZN(ZN),.A2(A2),.A1(A1));
`else
AOI22_X2_func AOI22_X2_inst(.B2(B2),.B1(B1),.ZN(ZN),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module AOI22_X4( B2, ZN, B1, A2, A1 );
input A1, A2, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
AOI22_X4_func AOI22_X4_behav_inst(.B2(B2),.ZN(ZN),.B1(B1),.A2(A2),.A1(A1));
`else
AOI22_X4_func AOI22_X4_inst(.B2(B2),.ZN(ZN),.B1(B1),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUFZ_X1( EN, I, Z );
input EN, I;
output Z;
`ifdef FUNCTIONAL // functional //
BUFZ_X1_func BUFZ_X1_behav_inst(.EN(EN),.I(I),.Z(Z));
`else
BUFZ_X1_func BUFZ_X1_inst(.EN(EN),.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> Z
(EN => Z) = (1.0,1.0);
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUFZ_X12( EN, I, Z );
input EN, I;
output Z;
`ifdef FUNCTIONAL // functional //
BUFZ_X12_func BUFZ_X12_behav_inst(.EN(EN),.I(I),.Z(Z));
`else
BUFZ_X12_func BUFZ_X12_inst(.EN(EN),.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> Z
(EN => Z) = (1.0,1.0);
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUFZ_X16( EN, I, Z );
input EN, I;
output Z;
`ifdef FUNCTIONAL // functional //
BUFZ_X16_func BUFZ_X16_behav_inst(.EN(EN),.I(I),.Z(Z));
`else
BUFZ_X16_func BUFZ_X16_inst(.EN(EN),.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> Z
(EN => Z) = (1.0,1.0);
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUFZ_X2( EN, I, Z );
input EN, I;
output Z;
`ifdef FUNCTIONAL // functional //
BUFZ_X2_func BUFZ_X2_behav_inst(.EN(EN),.I(I),.Z(Z));
`else
BUFZ_X2_func BUFZ_X2_inst(.EN(EN),.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> Z
(EN => Z) = (1.0,1.0);
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUFZ_X3( EN, I, Z );
input EN, I;
output Z;
`ifdef FUNCTIONAL // functional //
BUFZ_X3_func BUFZ_X3_behav_inst(.EN(EN),.I(I),.Z(Z));
`else
BUFZ_X3_func BUFZ_X3_inst(.EN(EN),.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> Z
(EN => Z) = (1.0,1.0);
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUFZ_X4( EN, I, Z );
input EN, I;
output Z;
`ifdef FUNCTIONAL // functional //
BUFZ_X4_func BUFZ_X4_behav_inst(.EN(EN),.I(I),.Z(Z));
`else
BUFZ_X4_func BUFZ_X4_inst(.EN(EN),.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> Z
(EN => Z) = (1.0,1.0);
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUFZ_X8( EN, I, Z );
input EN, I;
output Z;
`ifdef FUNCTIONAL // functional //
BUFZ_X8_func BUFZ_X8_behav_inst(.EN(EN),.I(I),.Z(Z));
`else
BUFZ_X8_func BUFZ_X8_inst(.EN(EN),.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> Z
(EN => Z) = (1.0,1.0);
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUF_X1( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
BUF_X1_func BUF_X1_behav_inst(.I(I),.Z(Z));
`else
BUF_X1_func BUF_X1_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUF_X12( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
BUF_X12_func BUF_X12_behav_inst(.I(I),.Z(Z));
`else
BUF_X12_func BUF_X12_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUF_X16( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
BUF_X16_func BUF_X16_behav_inst(.I(I),.Z(Z));
`else
BUF_X16_func BUF_X16_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUF_X2( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
BUF_X2_func BUF_X2_behav_inst(.I(I),.Z(Z));
`else
BUF_X2_func BUF_X2_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUF_X20( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
BUF_X20_func BUF_X20_behav_inst(.I(I),.Z(Z));
`else
BUF_X20_func BUF_X20_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUF_X3( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
BUF_X3_func BUF_X3_behav_inst(.I(I),.Z(Z));
`else
BUF_X3_func BUF_X3_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUF_X4( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
BUF_X4_func BUF_X4_behav_inst(.I(I),.Z(Z));
`else
BUF_X4_func BUF_X4_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module BUF_X8( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
BUF_X8_func BUF_X8_behav_inst(.I(I),.Z(Z));
`else
BUF_X8_func BUF_X8_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKBUF_X1( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
CLKBUF_X1_func CLKBUF_X1_behav_inst(.I(I),.Z(Z));
`else
CLKBUF_X1_func CLKBUF_X1_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKBUF_X12( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
CLKBUF_X12_func CLKBUF_X12_behav_inst(.I(I),.Z(Z));
`else
CLKBUF_X12_func CLKBUF_X12_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKBUF_X16( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
CLKBUF_X16_func CLKBUF_X16_behav_inst(.I(I),.Z(Z));
`else
CLKBUF_X16_func CLKBUF_X16_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKBUF_X2( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
CLKBUF_X2_func CLKBUF_X2_behav_inst(.I(I),.Z(Z));
`else
CLKBUF_X2_func CLKBUF_X2_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKBUF_X20( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
CLKBUF_X20_func CLKBUF_X20_behav_inst(.I(I),.Z(Z));
`else
CLKBUF_X20_func CLKBUF_X20_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKBUF_X3( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
CLKBUF_X3_func CLKBUF_X3_behav_inst(.I(I),.Z(Z));
`else
CLKBUF_X3_func CLKBUF_X3_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKBUF_X4( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
CLKBUF_X4_func CLKBUF_X4_behav_inst(.I(I),.Z(Z));
`else
CLKBUF_X4_func CLKBUF_X4_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKBUF_X8( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
CLKBUF_X8_func CLKBUF_X8_behav_inst(.I(I),.Z(Z));
`else
CLKBUF_X8_func CLKBUF_X8_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKINV_X1( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
CLKINV_X1_func CLKINV_X1_behav_inst(.I(I),.ZN(ZN));
`else
CLKINV_X1_func CLKINV_X1_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKINV_X12( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
CLKINV_X12_func CLKINV_X12_behav_inst(.I(I),.ZN(ZN));
`else
CLKINV_X12_func CLKINV_X12_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKINV_X16( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
CLKINV_X16_func CLKINV_X16_behav_inst(.I(I),.ZN(ZN));
`else
CLKINV_X16_func CLKINV_X16_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKINV_X2( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
CLKINV_X2_func CLKINV_X2_behav_inst(.I(I),.ZN(ZN));
`else
CLKINV_X2_func CLKINV_X2_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKINV_X20( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
CLKINV_X20_func CLKINV_X20_behav_inst(.I(I),.ZN(ZN));
`else
CLKINV_X20_func CLKINV_X20_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKINV_X3( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
CLKINV_X3_func CLKINV_X3_behav_inst(.I(I),.ZN(ZN));
`else
CLKINV_X3_func CLKINV_X3_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKINV_X4( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
CLKINV_X4_func CLKINV_X4_behav_inst(.I(I),.ZN(ZN));
`else
CLKINV_X4_func CLKINV_X4_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module CLKINV_X8( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
CLKINV_X8_func CLKINV_X8_behav_inst(.I(I),.ZN(ZN));
`else
CLKINV_X8_func CLKINV_X8_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNQ_X1( CLKN, D, Q );
input CLKN, D;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNQ_X1_func DFFNQ_X1_behav_inst(.CLKN(CLKN),.D(D),.Q(Q),.notifier(notifier));
`else
DFFNQ_X1_func DFFNQ_X1_inst(.CLKN(CLKN),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN,negedge D,1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN,posedge D,1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D,negedge CLKN,1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D,negedge CLKN,1.0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNQ_X2( CLKN, D, Q );
input CLKN, D;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNQ_X2_func DFFNQ_X2_behav_inst(.CLKN(CLKN),.D(D),.Q(Q),.notifier(notifier));
`else
DFFNQ_X2_func DFFNQ_X2_inst(.CLKN(CLKN),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN,negedge D,1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN,posedge D,1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D,negedge CLKN,1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D,negedge CLKN,1.0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNQ_X4( CLKN, D, Q );
input CLKN, D;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNQ_X4_func DFFNQ_X4_behav_inst(.CLKN(CLKN),.D(D),.Q(Q),.notifier(notifier));
`else
DFFNQ_X4_func DFFNQ_X4_inst(.CLKN(CLKN),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN,negedge D,1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN,posedge D,1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D,negedge CLKN,1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D,negedge CLKN,1.0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNRNQ_X1( CLKN, D, RN, Q );
input CLKN, D, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNRNQ_X1_func DFFNRNQ_X1_behav_inst(.CLKN(CLKN),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFNRNQ_X1_func DFFNRNQ_X1_inst(.CLKN(CLKN),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G2(ENABLE_D_AND_RN,RN,D);
buf MGM_G3(ENABLE_RN,RN);
not MGM_G4(MGM_W1,CLKN);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLKN);
and MGM_G8(ENABLE_NOT_CLKN_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLKN_AND_NOT_D,MGM_W4,CLKN);
and MGM_G11(ENABLE_CLKN_AND_D,D,CLKN);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// recovery RN-LH CLKN-HL
$recovery(posedge RN,negedge CLKN,1.0,notifier);
// removal RN-LH CLKN-HL
$removal(posedge RN,negedge CLKN,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNRNQ_X2( CLKN, D, RN, Q );
input CLKN, D, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNRNQ_X2_func DFFNRNQ_X2_behav_inst(.CLKN(CLKN),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFNRNQ_X2_func DFFNRNQ_X2_inst(.CLKN(CLKN),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G2(ENABLE_D_AND_RN,RN,D);
buf MGM_G3(ENABLE_RN,RN);
not MGM_G4(MGM_W1,CLKN);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLKN);
and MGM_G8(ENABLE_NOT_CLKN_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLKN_AND_NOT_D,MGM_W4,CLKN);
and MGM_G11(ENABLE_CLKN_AND_D,D,CLKN);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// recovery RN-LH CLKN-HL
$recovery(posedge RN,negedge CLKN,1.0,notifier);
// removal RN-LH CLKN-HL
$removal(posedge RN,negedge CLKN,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNRNQ_X4( CLKN, D, RN, Q );
input CLKN, D, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNRNQ_X4_func DFFNRNQ_X4_behav_inst(.CLKN(CLKN),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFNRNQ_X4_func DFFNRNQ_X4_inst(.CLKN(CLKN),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G2(ENABLE_D_AND_RN,RN,D);
buf MGM_G3(ENABLE_RN,RN);
not MGM_G4(MGM_W1,CLKN);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLKN);
and MGM_G8(ENABLE_NOT_CLKN_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLKN_AND_NOT_D,MGM_W4,CLKN);
and MGM_G11(ENABLE_CLKN_AND_D,D,CLKN);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// recovery RN-LH CLKN-HL
$recovery(posedge RN,negedge CLKN,1.0,notifier);
// removal RN-LH CLKN-HL
$removal(posedge RN,negedge CLKN,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNRSNQ_X1( CLKN, D, SETN, RN, Q );
input CLKN, D, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNRSNQ_X1_func DFFNRSNQ_X1_behav_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFNRSNQ_X1_func DFFNRSNQ_X1_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
and MGM_G2(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G3(MGM_W2,RN,D);
and MGM_G4(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
and MGM_G5(ENABLE_RN_AND_SETN,SETN,RN);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,CLKN);
not MGM_G8(MGM_W4,D);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_CLKN_AND_NOT_D_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,CLKN);
and MGM_G12(MGM_W7,D,MGM_W6);
and MGM_G13(ENABLE_NOT_CLKN_AND_D_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
and MGM_G15(MGM_W9,MGM_W8,CLKN);
and MGM_G16(ENABLE_CLKN_AND_NOT_D_AND_SETN,SETN,MGM_W9);
and MGM_G17(MGM_W10,D,CLKN);
and MGM_G18(ENABLE_CLKN_AND_D_AND_SETN,SETN,MGM_W10);
not MGM_G19(MGM_W11,CLKN);
not MGM_G20(MGM_W12,D);
and MGM_G21(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W12,MGM_W11);
not MGM_G22(MGM_W13,CLKN);
and MGM_G23(ENABLE_NOT_CLKN_AND_D,D,MGM_W13);
not MGM_G24(MGM_W14,D);
and MGM_G25(ENABLE_CLKN_AND_NOT_D,MGM_W14,CLKN);
and MGM_G26(ENABLE_CLKN_AND_D,D,CLKN);
buf MGM_G27(ENABLE_RN,RN);
not MGM_G28(MGM_W15,CLKN);
not MGM_G29(MGM_W16,D);
and MGM_G30(MGM_W17,MGM_W16,MGM_W15);
and MGM_G31(ENABLE_NOT_CLKN_AND_NOT_D_AND_RN,RN,MGM_W17);
not MGM_G32(MGM_W18,CLKN);
and MGM_G33(MGM_W19,D,MGM_W18);
and MGM_G34(ENABLE_NOT_CLKN_AND_D_AND_RN,RN,MGM_W19);
not MGM_G35(MGM_W20,D);
and MGM_G36(MGM_W21,MGM_W20,CLKN);
and MGM_G37(ENABLE_CLKN_AND_NOT_D_AND_RN,RN,MGM_W21);
and MGM_G38(MGM_W22,D,CLKN);
and MGM_G39(ENABLE_CLKN_AND_D_AND_RN,RN,MGM_W22);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// recovery RN-LH CLKN-HL
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH CLKN-HL
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// recovery SETN-LH CLKN-HL
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH CLKN-HL
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNRSNQ_X2( CLKN, D, SETN, RN, Q );
input CLKN, D, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNRSNQ_X2_func DFFNRSNQ_X2_behav_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFNRSNQ_X2_func DFFNRSNQ_X2_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
and MGM_G2(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G3(MGM_W2,RN,D);
and MGM_G4(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
and MGM_G5(ENABLE_RN_AND_SETN,SETN,RN);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,CLKN);
not MGM_G8(MGM_W4,D);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_CLKN_AND_NOT_D_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,CLKN);
and MGM_G12(MGM_W7,D,MGM_W6);
and MGM_G13(ENABLE_NOT_CLKN_AND_D_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
and MGM_G15(MGM_W9,MGM_W8,CLKN);
and MGM_G16(ENABLE_CLKN_AND_NOT_D_AND_SETN,SETN,MGM_W9);
and MGM_G17(MGM_W10,D,CLKN);
and MGM_G18(ENABLE_CLKN_AND_D_AND_SETN,SETN,MGM_W10);
not MGM_G19(MGM_W11,CLKN);
not MGM_G20(MGM_W12,D);
and MGM_G21(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W12,MGM_W11);
not MGM_G22(MGM_W13,CLKN);
and MGM_G23(ENABLE_NOT_CLKN_AND_D,D,MGM_W13);
not MGM_G24(MGM_W14,D);
and MGM_G25(ENABLE_CLKN_AND_NOT_D,MGM_W14,CLKN);
and MGM_G26(ENABLE_CLKN_AND_D,D,CLKN);
buf MGM_G27(ENABLE_RN,RN);
not MGM_G28(MGM_W15,CLKN);
not MGM_G29(MGM_W16,D);
and MGM_G30(MGM_W17,MGM_W16,MGM_W15);
and MGM_G31(ENABLE_NOT_CLKN_AND_NOT_D_AND_RN,RN,MGM_W17);
not MGM_G32(MGM_W18,CLKN);
and MGM_G33(MGM_W19,D,MGM_W18);
and MGM_G34(ENABLE_NOT_CLKN_AND_D_AND_RN,RN,MGM_W19);
not MGM_G35(MGM_W20,D);
and MGM_G36(MGM_W21,MGM_W20,CLKN);
and MGM_G37(ENABLE_CLKN_AND_NOT_D_AND_RN,RN,MGM_W21);
and MGM_G38(MGM_W22,D,CLKN);
and MGM_G39(ENABLE_CLKN_AND_D_AND_RN,RN,MGM_W22);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// recovery RN-LH CLKN-HL
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH CLKN-HL
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// recovery SETN-LH CLKN-HL
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH CLKN-HL
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNRSNQ_X4( CLKN, D, SETN, RN, Q );
input CLKN, D, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNRSNQ_X4_func DFFNRSNQ_X4_behav_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFNRSNQ_X4_func DFFNRSNQ_X4_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
and MGM_G2(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G3(MGM_W2,RN,D);
and MGM_G4(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
and MGM_G5(ENABLE_RN_AND_SETN,SETN,RN);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,CLKN);
not MGM_G8(MGM_W4,D);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_CLKN_AND_NOT_D_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,CLKN);
and MGM_G12(MGM_W7,D,MGM_W6);
and MGM_G13(ENABLE_NOT_CLKN_AND_D_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
and MGM_G15(MGM_W9,MGM_W8,CLKN);
and MGM_G16(ENABLE_CLKN_AND_NOT_D_AND_SETN,SETN,MGM_W9);
and MGM_G17(MGM_W10,D,CLKN);
and MGM_G18(ENABLE_CLKN_AND_D_AND_SETN,SETN,MGM_W10);
not MGM_G19(MGM_W11,CLKN);
not MGM_G20(MGM_W12,D);
and MGM_G21(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W12,MGM_W11);
not MGM_G22(MGM_W13,CLKN);
and MGM_G23(ENABLE_NOT_CLKN_AND_D,D,MGM_W13);
not MGM_G24(MGM_W14,D);
and MGM_G25(ENABLE_CLKN_AND_NOT_D,MGM_W14,CLKN);
and MGM_G26(ENABLE_CLKN_AND_D,D,CLKN);
buf MGM_G27(ENABLE_RN,RN);
not MGM_G28(MGM_W15,CLKN);
not MGM_G29(MGM_W16,D);
and MGM_G30(MGM_W17,MGM_W16,MGM_W15);
and MGM_G31(ENABLE_NOT_CLKN_AND_NOT_D_AND_RN,RN,MGM_W17);
not MGM_G32(MGM_W18,CLKN);
and MGM_G33(MGM_W19,D,MGM_W18);
and MGM_G34(ENABLE_NOT_CLKN_AND_D_AND_RN,RN,MGM_W19);
not MGM_G35(MGM_W20,D);
and MGM_G36(MGM_W21,MGM_W20,CLKN);
and MGM_G37(ENABLE_CLKN_AND_NOT_D_AND_RN,RN,MGM_W21);
and MGM_G38(MGM_W22,D,CLKN);
and MGM_G39(ENABLE_CLKN_AND_D_AND_RN,RN,MGM_W22);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge CLKN &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// recovery RN-LH CLKN-HL
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH CLKN-HL
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLKN_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLKN_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// recovery SETN-LH CLKN-HL
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH CLKN-HL
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge CLKN &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLKN_AND_D === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNSNQ_X1( CLKN, D, SETN, Q );
input CLKN, D, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNSNQ_X1_func DFFNSNQ_X1_behav_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
DFFNSNQ_X1_func DFFNSNQ_X1_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G2(ENABLE_D_AND_SETN,SETN,D);
buf MGM_G3(ENABLE_SETN,SETN);
not MGM_G4(MGM_W1,CLKN);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLKN);
and MGM_G8(ENABLE_NOT_CLKN_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLKN_AND_NOT_D,MGM_W4,CLKN);
and MGM_G11(ENABLE_CLKN_AND_D,D,CLKN);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// recovery SETN-LH CLKN-HL
$recovery(posedge SETN,negedge CLKN,1.0,notifier);
// removal SETN-LH CLKN-HL
$removal(posedge SETN,negedge CLKN,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNSNQ_X2( CLKN, D, SETN, Q );
input CLKN, D, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNSNQ_X2_func DFFNSNQ_X2_behav_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
DFFNSNQ_X2_func DFFNSNQ_X2_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G2(ENABLE_D_AND_SETN,SETN,D);
buf MGM_G3(ENABLE_SETN,SETN);
not MGM_G4(MGM_W1,CLKN);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLKN);
and MGM_G8(ENABLE_NOT_CLKN_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLKN_AND_NOT_D,MGM_W4,CLKN);
and MGM_G11(ENABLE_CLKN_AND_D,D,CLKN);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// recovery SETN-LH CLKN-HL
$recovery(posedge SETN,negedge CLKN,1.0,notifier);
// removal SETN-LH CLKN-HL
$removal(posedge SETN,negedge CLKN,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFNSNQ_X4( CLKN, D, SETN, Q );
input CLKN, D, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFNSNQ_X4_func DFFNSNQ_X4_behav_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
DFFNSNQ_X4_func DFFNSNQ_X4_inst(.CLKN(CLKN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G2(ENABLE_D_AND_SETN,SETN,D);
buf MGM_G3(ENABLE_SETN,SETN);
not MGM_G4(MGM_W1,CLKN);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLKN_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLKN);
and MGM_G8(ENABLE_NOT_CLKN_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLKN_AND_NOT_D,MGM_W4,CLKN);
and MGM_G11(ENABLE_CLKN_AND_D,D,CLKN);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLKN --> Q
(negedge CLKN => (Q : D)) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLKN===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLKN-HL
$hold(negedge CLKN &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH CLKN-HL
$hold(negedge CLKN &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL CLKN-HL
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH CLKN-HL
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
negedge CLKN &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// recovery SETN-LH CLKN-HL
$recovery(posedge SETN,negedge CLKN,1.0,notifier);
// removal SETN-LH CLKN-HL
$removal(posedge SETN,negedge CLKN,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLKN_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// mpw CLKN_hl
$width(negedge CLKN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(negedge CLKN &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLKN
$period(posedge CLKN,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFQ_X1( CLK, D, Q );
input CLK, D;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFQ_X1_func DFFQ_X1_behav_inst(.CLK(CLK),.D(D),.Q(Q),.notifier(notifier));
`else
DFFQ_X1_func DFFQ_X1_inst(.CLK(CLK),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK,negedge D,1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK,posedge D,1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D,posedge CLK,1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D,posedge CLK,1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFQ_X2( CLK, D, Q );
input CLK, D;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFQ_X2_func DFFQ_X2_behav_inst(.CLK(CLK),.D(D),.Q(Q),.notifier(notifier));
`else
DFFQ_X2_func DFFQ_X2_inst(.CLK(CLK),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK,negedge D,1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK,posedge D,1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D,posedge CLK,1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D,posedge CLK,1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFQ_X4( CLK, D, Q );
input CLK, D;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFQ_X4_func DFFQ_X4_behav_inst(.CLK(CLK),.D(D),.Q(Q),.notifier(notifier));
`else
DFFQ_X4_func DFFQ_X4_inst(.CLK(CLK),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK,negedge D,1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK,posedge D,1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D,posedge CLK,1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D,posedge CLK,1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFRNQ_X1( CLK, D, RN, Q );
input CLK, D, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFRNQ_X1_func DFFRNQ_X1_behav_inst(.CLK(CLK),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFRNQ_X1_func DFFRNQ_X1_inst(.CLK(CLK),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G2(ENABLE_D_AND_RN,RN,D);
buf MGM_G3(ENABLE_RN,RN);
not MGM_G4(MGM_W1,CLK);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLK_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLK);
and MGM_G8(ENABLE_NOT_CLK_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLK_AND_NOT_D,MGM_W4,CLK);
and MGM_G11(ENABLE_CLK_AND_D,D,CLK);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN,posedge CLK,1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN,posedge CLK,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFRNQ_X2( CLK, D, RN, Q );
input CLK, D, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFRNQ_X2_func DFFRNQ_X2_behav_inst(.CLK(CLK),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFRNQ_X2_func DFFRNQ_X2_inst(.CLK(CLK),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G2(ENABLE_D_AND_RN,RN,D);
buf MGM_G3(ENABLE_RN,RN);
not MGM_G4(MGM_W1,CLK);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLK_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLK);
and MGM_G8(ENABLE_NOT_CLK_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLK_AND_NOT_D,MGM_W4,CLK);
and MGM_G11(ENABLE_CLK_AND_D,D,CLK);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN,posedge CLK,1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN,posedge CLK,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFRNQ_X4( CLK, D, RN, Q );
input CLK, D, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFRNQ_X4_func DFFRNQ_X4_behav_inst(.CLK(CLK),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFRNQ_X4_func DFFRNQ_X4_inst(.CLK(CLK),.D(D),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G2(ENABLE_D_AND_RN,RN,D);
buf MGM_G3(ENABLE_RN,RN);
not MGM_G4(MGM_W1,CLK);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLK_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLK);
and MGM_G8(ENABLE_NOT_CLK_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLK_AND_NOT_D,MGM_W4,CLK);
and MGM_G11(ENABLE_CLK_AND_D,D,CLK);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN,posedge CLK,1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN,posedge CLK,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFRSNQ_X1( CLK, D, SETN, RN, Q );
input CLK, D, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFRSNQ_X1_func DFFRSNQ_X1_behav_inst(.CLK(CLK),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFRSNQ_X1_func DFFRSNQ_X1_inst(.CLK(CLK),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
and MGM_G2(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G3(MGM_W2,RN,D);
and MGM_G4(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
and MGM_G5(ENABLE_RN_AND_SETN,SETN,RN);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,CLK);
not MGM_G8(MGM_W4,D);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_CLK_AND_NOT_D_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,CLK);
and MGM_G12(MGM_W7,D,MGM_W6);
and MGM_G13(ENABLE_NOT_CLK_AND_D_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
and MGM_G15(MGM_W9,MGM_W8,CLK);
and MGM_G16(ENABLE_CLK_AND_NOT_D_AND_SETN,SETN,MGM_W9);
and MGM_G17(MGM_W10,D,CLK);
and MGM_G18(ENABLE_CLK_AND_D_AND_SETN,SETN,MGM_W10);
not MGM_G19(MGM_W11,CLK);
not MGM_G20(MGM_W12,D);
and MGM_G21(ENABLE_NOT_CLK_AND_NOT_D,MGM_W12,MGM_W11);
not MGM_G22(MGM_W13,CLK);
and MGM_G23(ENABLE_NOT_CLK_AND_D,D,MGM_W13);
not MGM_G24(MGM_W14,D);
and MGM_G25(ENABLE_CLK_AND_NOT_D,MGM_W14,CLK);
and MGM_G26(ENABLE_CLK_AND_D,D,CLK);
buf MGM_G27(ENABLE_RN,RN);
not MGM_G28(MGM_W15,CLK);
not MGM_G29(MGM_W16,D);
and MGM_G30(MGM_W17,MGM_W16,MGM_W15);
and MGM_G31(ENABLE_NOT_CLK_AND_NOT_D_AND_RN,RN,MGM_W17);
not MGM_G32(MGM_W18,CLK);
and MGM_G33(MGM_W19,D,MGM_W18);
and MGM_G34(ENABLE_NOT_CLK_AND_D_AND_RN,RN,MGM_W19);
not MGM_G35(MGM_W20,D);
and MGM_G36(MGM_W21,MGM_W20,CLK);
and MGM_G37(ENABLE_CLK_AND_NOT_D_AND_RN,RN,MGM_W21);
and MGM_G38(MGM_W22,D,CLK);
and MGM_G39(ENABLE_CLK_AND_D_AND_RN,RN,MGM_W22);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFRSNQ_X2( CLK, D, SETN, RN, Q );
input CLK, D, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFRSNQ_X2_func DFFRSNQ_X2_behav_inst(.CLK(CLK),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFRSNQ_X2_func DFFRSNQ_X2_inst(.CLK(CLK),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
and MGM_G2(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G3(MGM_W2,RN,D);
and MGM_G4(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
and MGM_G5(ENABLE_RN_AND_SETN,SETN,RN);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,CLK);
not MGM_G8(MGM_W4,D);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_CLK_AND_NOT_D_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,CLK);
and MGM_G12(MGM_W7,D,MGM_W6);
and MGM_G13(ENABLE_NOT_CLK_AND_D_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
and MGM_G15(MGM_W9,MGM_W8,CLK);
and MGM_G16(ENABLE_CLK_AND_NOT_D_AND_SETN,SETN,MGM_W9);
and MGM_G17(MGM_W10,D,CLK);
and MGM_G18(ENABLE_CLK_AND_D_AND_SETN,SETN,MGM_W10);
not MGM_G19(MGM_W11,CLK);
not MGM_G20(MGM_W12,D);
and MGM_G21(ENABLE_NOT_CLK_AND_NOT_D,MGM_W12,MGM_W11);
not MGM_G22(MGM_W13,CLK);
and MGM_G23(ENABLE_NOT_CLK_AND_D,D,MGM_W13);
not MGM_G24(MGM_W14,D);
and MGM_G25(ENABLE_CLK_AND_NOT_D,MGM_W14,CLK);
and MGM_G26(ENABLE_CLK_AND_D,D,CLK);
buf MGM_G27(ENABLE_RN,RN);
not MGM_G28(MGM_W15,CLK);
not MGM_G29(MGM_W16,D);
and MGM_G30(MGM_W17,MGM_W16,MGM_W15);
and MGM_G31(ENABLE_NOT_CLK_AND_NOT_D_AND_RN,RN,MGM_W17);
not MGM_G32(MGM_W18,CLK);
and MGM_G33(MGM_W19,D,MGM_W18);
and MGM_G34(ENABLE_NOT_CLK_AND_D_AND_RN,RN,MGM_W19);
not MGM_G35(MGM_W20,D);
and MGM_G36(MGM_W21,MGM_W20,CLK);
and MGM_G37(ENABLE_CLK_AND_NOT_D_AND_RN,RN,MGM_W21);
and MGM_G38(MGM_W22,D,CLK);
and MGM_G39(ENABLE_CLK_AND_D_AND_RN,RN,MGM_W22);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFRSNQ_X4( CLK, D, SETN, RN, Q );
input CLK, D, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFRSNQ_X4_func DFFRSNQ_X4_behav_inst(.CLK(CLK),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
DFFRSNQ_X4_func DFFRSNQ_X4_inst(.CLK(CLK),.D(D),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
and MGM_G2(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G3(MGM_W2,RN,D);
and MGM_G4(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
and MGM_G5(ENABLE_RN_AND_SETN,SETN,RN);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,CLK);
not MGM_G8(MGM_W4,D);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_CLK_AND_NOT_D_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,CLK);
and MGM_G12(MGM_W7,D,MGM_W6);
and MGM_G13(ENABLE_NOT_CLK_AND_D_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
and MGM_G15(MGM_W9,MGM_W8,CLK);
and MGM_G16(ENABLE_CLK_AND_NOT_D_AND_SETN,SETN,MGM_W9);
and MGM_G17(MGM_W10,D,CLK);
and MGM_G18(ENABLE_CLK_AND_D_AND_SETN,SETN,MGM_W10);
not MGM_G19(MGM_W11,CLK);
not MGM_G20(MGM_W12,D);
and MGM_G21(ENABLE_NOT_CLK_AND_NOT_D,MGM_W12,MGM_W11);
not MGM_G22(MGM_W13,CLK);
and MGM_G23(ENABLE_NOT_CLK_AND_D,D,MGM_W13);
not MGM_G24(MGM_W14,D);
and MGM_G25(ENABLE_CLK_AND_NOT_D,MGM_W14,CLK);
and MGM_G26(ENABLE_CLK_AND_D,D,CLK);
buf MGM_G27(ENABLE_RN,RN);
not MGM_G28(MGM_W15,CLK);
not MGM_G29(MGM_W16,D);
and MGM_G30(MGM_W17,MGM_W16,MGM_W15);
and MGM_G31(ENABLE_NOT_CLK_AND_NOT_D_AND_RN,RN,MGM_W17);
not MGM_G32(MGM_W18,CLK);
and MGM_G33(MGM_W19,D,MGM_W18);
and MGM_G34(ENABLE_NOT_CLK_AND_D_AND_RN,RN,MGM_W19);
not MGM_G35(MGM_W20,D);
and MGM_G36(MGM_W21,MGM_W20,CLK);
and MGM_G37(ENABLE_CLK_AND_NOT_D_AND_RN,RN,MGM_W21);
and MGM_G38(MGM_W22,D,CLK);
and MGM_G39(ENABLE_CLK_AND_D_AND_RN,RN,MGM_W22);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SETN===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SETN===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
posedge CLK &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFSNQ_X1( CLK, D, SETN, Q );
input CLK, D, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFSNQ_X1_func DFFSNQ_X1_behav_inst(.CLK(CLK),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
DFFSNQ_X1_func DFFSNQ_X1_inst(.CLK(CLK),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G2(ENABLE_D_AND_SETN,SETN,D);
buf MGM_G3(ENABLE_SETN,SETN);
not MGM_G4(MGM_W1,CLK);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLK_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLK);
and MGM_G8(ENABLE_NOT_CLK_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLK_AND_NOT_D,MGM_W4,CLK);
and MGM_G11(ENABLE_CLK_AND_D,D,CLK);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN,posedge CLK,1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN,posedge CLK,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFSNQ_X2( CLK, D, SETN, Q );
input CLK, D, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFSNQ_X2_func DFFSNQ_X2_behav_inst(.CLK(CLK),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
DFFSNQ_X2_func DFFSNQ_X2_inst(.CLK(CLK),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G2(ENABLE_D_AND_SETN,SETN,D);
buf MGM_G3(ENABLE_SETN,SETN);
not MGM_G4(MGM_W1,CLK);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLK_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLK);
and MGM_G8(ENABLE_NOT_CLK_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLK_AND_NOT_D,MGM_W4,CLK);
and MGM_G11(ENABLE_CLK_AND_D,D,CLK);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN,posedge CLK,1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN,posedge CLK,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DFFSNQ_X4( CLK, D, SETN, Q );
input CLK, D, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
DFFSNQ_X4_func DFFSNQ_X4_behav_inst(.CLK(CLK),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
DFFSNQ_X4_func DFFSNQ_X4_inst(.CLK(CLK),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G2(ENABLE_D_AND_SETN,SETN,D);
buf MGM_G3(ENABLE_SETN,SETN);
not MGM_G4(MGM_W1,CLK);
not MGM_G5(MGM_W2,D);
and MGM_G6(ENABLE_NOT_CLK_AND_NOT_D,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,CLK);
and MGM_G8(ENABLE_NOT_CLK_AND_D,D,MGM_W3);
not MGM_G9(MGM_W4,D);
and MGM_G10(ENABLE_CLK_AND_NOT_D,MGM_W4,CLK);
and MGM_G11(ENABLE_CLK_AND_D,D,CLK);
// spec_gates_end
specify
// specify_block_begin
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
posedge CLK &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN,posedge CLK,1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN,posedge CLK,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D === 1'b1)
,1.0,0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYA_X1( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYA_X1_func DLYA_X1_behav_inst(.I(I),.Z(Z));
`else
DLYA_X1_func DLYA_X1_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYA_X2( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYA_X2_func DLYA_X2_behav_inst(.I(I),.Z(Z));
`else
DLYA_X2_func DLYA_X2_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYA_X4( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYA_X4_func DLYA_X4_behav_inst(.I(I),.Z(Z));
`else
DLYA_X4_func DLYA_X4_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYB_X1( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYB_X1_func DLYB_X1_behav_inst(.I(I),.Z(Z));
`else
DLYB_X1_func DLYB_X1_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYB_X2( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYB_X2_func DLYB_X2_behav_inst(.I(I),.Z(Z));
`else
DLYB_X2_func DLYB_X2_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYB_X4( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYB_X4_func DLYB_X4_behav_inst(.I(I),.Z(Z));
`else
DLYB_X4_func DLYB_X4_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYC_X1( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYC_X1_func DLYC_X1_behav_inst(.I(I),.Z(Z));
`else
DLYC_X1_func DLYC_X1_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYC_X2( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYC_X2_func DLYC_X2_behav_inst(.I(I),.Z(Z));
`else
DLYC_X2_func DLYC_X2_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYC_X4( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYC_X4_func DLYC_X4_behav_inst(.I(I),.Z(Z));
`else
DLYC_X4_func DLYC_X4_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYD_X1( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYD_X1_func DLYD_X1_behav_inst(.I(I),.Z(Z));
`else
DLYD_X1_func DLYD_X1_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYD_X2( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYD_X2_func DLYD_X2_behav_inst(.I(I),.Z(Z));
`else
DLYD_X2_func DLYD_X2_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module DLYD_X4( I, Z );
input I;
output Z;
`ifdef FUNCTIONAL // functional //
DLYD_X4_func DLYD_X4_behav_inst(.I(I),.Z(Z));
`else
DLYD_X4_func DLYD_X4_inst(.I(I),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> Z
(I => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ENDCAP( );
`ifdef FUNCTIONAL // functional //
ENDCAP_func ENDCAP_behav_inst();
`else
ENDCAP_func ENDCAP_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILLCAP_X16( );
`ifdef FUNCTIONAL // functional //
FILLCAP_X16_func FILLCAP_X16_behav_inst();
`else
FILLCAP_X16_func FILLCAP_X16_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILLCAP_X32( );
`ifdef FUNCTIONAL // functional //
FILLCAP_X32_func FILLCAP_X32_behav_inst();
`else
FILLCAP_X32_func FILLCAP_X32_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILLCAP_X4( );
`ifdef FUNCTIONAL // functional //
FILLCAP_X4_func FILLCAP_X4_behav_inst();
`else
FILLCAP_X4_func FILLCAP_X4_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILLCAP_X64( );
`ifdef FUNCTIONAL // functional //
FILLCAP_X64_func FILLCAP_X64_behav_inst();
`else
FILLCAP_X64_func FILLCAP_X64_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILLCAP_X8( );
`ifdef FUNCTIONAL // functional //
FILLCAP_X8_func FILLCAP_X8_behav_inst();
`else
FILLCAP_X8_func FILLCAP_X8_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILLTIE( );
`ifdef FUNCTIONAL // functional //
FILLTIE_func FILLTIE_behav_inst();
`else
FILLTIE_func FILLTIE_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILL_X1( );
`ifdef FUNCTIONAL // functional //
FILL_X1_func FILL_X1_behav_inst();
`else
FILL_X1_func FILL_X1_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILL_X16( );
`ifdef FUNCTIONAL // functional //
FILL_X16_func FILL_X16_behav_inst();
`else
FILL_X16_func FILL_X16_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILL_X2( );
`ifdef FUNCTIONAL // functional //
FILL_X2_func FILL_X2_behav_inst();
`else
FILL_X2_func FILL_X2_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILL_X32( );
`ifdef FUNCTIONAL // functional //
FILL_X32_func FILL_X32_behav_inst();
`else
FILL_X32_func FILL_X32_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILL_X4( );
`ifdef FUNCTIONAL // functional //
FILL_X4_func FILL_X4_behav_inst();
`else
FILL_X4_func FILL_X4_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILL_X64( );
`ifdef FUNCTIONAL // functional //
FILL_X64_func FILL_X64_behav_inst();
`else
FILL_X64_func FILL_X64_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module FILL_X8( );
`ifdef FUNCTIONAL // functional //
FILL_X8_func FILL_X8_behav_inst();
`else
FILL_X8_func FILL_X8_inst();
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module HOLD( Z );
inout Z;
`ifdef FUNCTIONAL // functional //
HOLD_func HOLD_behav_inst(.Z(Z));
`else
HOLD_func HOLD_inst(.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ICGTN_X1( TE, E, CLKN, Q );
input CLKN, E, TE;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
ICGTN_X1_func ICGTN_X1_behav_inst(.TE(TE),.E(E),.CLKN(CLKN),.Q(Q),.notifier(notifier));
`else
ICGTN_X1_func ICGTN_X1_inst(.TE(TE),.E(E),.CLKN(CLKN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,E);
not MGM_G1(MGM_W1,TE);
and MGM_G2(ENABLE_NOT_E_AND_NOT_TE,MGM_W1,MGM_W0);
not MGM_G3(MGM_W2,E);
and MGM_G4(ENABLE_NOT_E_AND_TE,TE,MGM_W2);
not MGM_G5(MGM_W3,TE);
and MGM_G6(ENABLE_E_AND_NOT_TE,MGM_W3,E);
and MGM_G7(ENABLE_E_AND_TE,TE,E);
// spec_gates_end
specify
// specify_block_begin
if(E===1'b0 && TE===1'b1)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b0)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b1)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
ifnone
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b0 && TE===1'b0)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
$width(posedge CLKN &&& (ENABLE_NOT_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_E_AND_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_E_AND_TE === 1'b1)
,1.0,0,notifier);
// hold E-HL CLKN-HL
$hold(negedge CLKN,negedge E,1.0,notifier);
// hold E-LH CLKN-HL
$hold(negedge CLKN,posedge E,1.0,notifier);
// setup E-HL CLKN-HL
$setup(negedge E,negedge CLKN,1.0,notifier);
// setup E-LH CLKN-HL
$setup(posedge E,negedge CLKN,1.0,notifier);
// hold TE-HL CLKN-HL
$hold(negedge CLKN,negedge TE,1.0,notifier);
// hold TE-LH CLKN-HL
$hold(negedge CLKN,posedge TE,1.0,notifier);
// setup TE-HL CLKN-HL
$setup(negedge TE,negedge CLKN,1.0,notifier);
// setup TE-LH CLKN-HL
$setup(posedge TE,negedge CLKN,1.0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ICGTN_X2( TE, E, CLKN, Q );
input CLKN, E, TE;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
ICGTN_X2_func ICGTN_X2_behav_inst(.TE(TE),.E(E),.CLKN(CLKN),.Q(Q),.notifier(notifier));
`else
ICGTN_X2_func ICGTN_X2_inst(.TE(TE),.E(E),.CLKN(CLKN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,E);
not MGM_G1(MGM_W1,TE);
and MGM_G2(ENABLE_NOT_E_AND_NOT_TE,MGM_W1,MGM_W0);
not MGM_G3(MGM_W2,E);
and MGM_G4(ENABLE_NOT_E_AND_TE,TE,MGM_W2);
not MGM_G5(MGM_W3,TE);
and MGM_G6(ENABLE_E_AND_NOT_TE,MGM_W3,E);
and MGM_G7(ENABLE_E_AND_TE,TE,E);
// spec_gates_end
specify
// specify_block_begin
if(E===1'b0 && TE===1'b1)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b0)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b1)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
ifnone
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b0 && TE===1'b0)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
$width(posedge CLKN &&& (ENABLE_NOT_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_E_AND_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_E_AND_TE === 1'b1)
,1.0,0,notifier);
// hold E-HL CLKN-HL
$hold(negedge CLKN,negedge E,1.0,notifier);
// hold E-LH CLKN-HL
$hold(negedge CLKN,posedge E,1.0,notifier);
// setup E-HL CLKN-HL
$setup(negedge E,negedge CLKN,1.0,notifier);
// setup E-LH CLKN-HL
$setup(posedge E,negedge CLKN,1.0,notifier);
// hold TE-HL CLKN-HL
$hold(negedge CLKN,negedge TE,1.0,notifier);
// hold TE-LH CLKN-HL
$hold(negedge CLKN,posedge TE,1.0,notifier);
// setup TE-HL CLKN-HL
$setup(negedge TE,negedge CLKN,1.0,notifier);
// setup TE-LH CLKN-HL
$setup(posedge TE,negedge CLKN,1.0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ICGTN_X4( TE, E, CLKN, Q );
input CLKN, E, TE;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
ICGTN_X4_func ICGTN_X4_behav_inst(.TE(TE),.E(E),.CLKN(CLKN),.Q(Q),.notifier(notifier));
`else
ICGTN_X4_func ICGTN_X4_inst(.TE(TE),.E(E),.CLKN(CLKN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,E);
not MGM_G1(MGM_W1,TE);
and MGM_G2(ENABLE_NOT_E_AND_NOT_TE,MGM_W1,MGM_W0);
not MGM_G3(MGM_W2,E);
and MGM_G4(ENABLE_NOT_E_AND_TE,TE,MGM_W2);
not MGM_G5(MGM_W3,TE);
and MGM_G6(ENABLE_E_AND_NOT_TE,MGM_W3,E);
and MGM_G7(ENABLE_E_AND_TE,TE,E);
// spec_gates_end
specify
// specify_block_begin
if(E===1'b0 && TE===1'b1)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b0)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b1)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
ifnone
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
if(E===1'b0 && TE===1'b0)
// comb arc CLKN --> Q
(CLKN => Q) = (1.0,1.0);
$width(posedge CLKN &&& (ENABLE_NOT_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_NOT_E_AND_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(posedge CLKN &&& (ENABLE_E_AND_TE === 1'b1)
,1.0,0,notifier);
// hold E-HL CLKN-HL
$hold(negedge CLKN,negedge E,1.0,notifier);
// hold E-LH CLKN-HL
$hold(negedge CLKN,posedge E,1.0,notifier);
// setup E-HL CLKN-HL
$setup(negedge E,negedge CLKN,1.0,notifier);
// setup E-LH CLKN-HL
$setup(posedge E,negedge CLKN,1.0,notifier);
// hold TE-HL CLKN-HL
$hold(negedge CLKN,negedge TE,1.0,notifier);
// hold TE-LH CLKN-HL
$hold(negedge CLKN,posedge TE,1.0,notifier);
// setup TE-HL CLKN-HL
$setup(negedge TE,negedge CLKN,1.0,notifier);
// setup TE-LH CLKN-HL
$setup(posedge TE,negedge CLKN,1.0,notifier);
// mpw CLKN_lh
$width(posedge CLKN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ICGTP_X1( TE, E, CLK, Q );
input CLK, E, TE;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
ICGTP_X1_func ICGTP_X1_behav_inst(.TE(TE),.E(E),.CLK(CLK),.Q(Q),.notifier(notifier));
`else
ICGTP_X1_func ICGTP_X1_inst(.TE(TE),.E(E),.CLK(CLK),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,E);
not MGM_G1(MGM_W1,TE);
and MGM_G2(ENABLE_NOT_E_AND_NOT_TE,MGM_W1,MGM_W0);
not MGM_G3(MGM_W2,E);
and MGM_G4(ENABLE_NOT_E_AND_TE,TE,MGM_W2);
not MGM_G5(MGM_W3,TE);
and MGM_G6(ENABLE_E_AND_NOT_TE,MGM_W3,E);
and MGM_G7(ENABLE_E_AND_TE,TE,E);
// spec_gates_end
specify
// specify_block_begin
if(E===1'b0 && TE===1'b1)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b0)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b1)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
ifnone
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b0 && TE===1'b0)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_E_AND_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_E_AND_TE === 1'b1)
,1.0,0,notifier);
// hold E-HL CLK-LH
$hold(posedge CLK,negedge E,1.0,notifier);
// hold E-LH CLK-LH
$hold(posedge CLK,posedge E,1.0,notifier);
// setup E-HL CLK-LH
$setup(negedge E,posedge CLK,1.0,notifier);
// setup E-LH CLK-LH
$setup(posedge E,posedge CLK,1.0,notifier);
// hold TE-HL CLK-LH
$hold(posedge CLK,negedge TE,1.0,notifier);
// hold TE-LH CLK-LH
$hold(posedge CLK,posedge TE,1.0,notifier);
// setup TE-HL CLK-LH
$setup(negedge TE,posedge CLK,1.0,notifier);
// setup TE-LH CLK-LH
$setup(posedge TE,posedge CLK,1.0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ICGTP_X2( TE, E, CLK, Q );
input CLK, E, TE;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
ICGTP_X2_func ICGTP_X2_behav_inst(.TE(TE),.E(E),.CLK(CLK),.Q(Q),.notifier(notifier));
`else
ICGTP_X2_func ICGTP_X2_inst(.TE(TE),.E(E),.CLK(CLK),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,E);
not MGM_G1(MGM_W1,TE);
and MGM_G2(ENABLE_NOT_E_AND_NOT_TE,MGM_W1,MGM_W0);
not MGM_G3(MGM_W2,E);
and MGM_G4(ENABLE_NOT_E_AND_TE,TE,MGM_W2);
not MGM_G5(MGM_W3,TE);
and MGM_G6(ENABLE_E_AND_NOT_TE,MGM_W3,E);
and MGM_G7(ENABLE_E_AND_TE,TE,E);
// spec_gates_end
specify
// specify_block_begin
if(E===1'b0 && TE===1'b1)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b0)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b1)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
ifnone
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b0 && TE===1'b0)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_E_AND_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_E_AND_TE === 1'b1)
,1.0,0,notifier);
// hold E-HL CLK-LH
$hold(posedge CLK,negedge E,1.0,notifier);
// hold E-LH CLK-LH
$hold(posedge CLK,posedge E,1.0,notifier);
// setup E-HL CLK-LH
$setup(negedge E,posedge CLK,1.0,notifier);
// setup E-LH CLK-LH
$setup(posedge E,posedge CLK,1.0,notifier);
// hold TE-HL CLK-LH
$hold(posedge CLK,negedge TE,1.0,notifier);
// hold TE-LH CLK-LH
$hold(posedge CLK,posedge TE,1.0,notifier);
// setup TE-HL CLK-LH
$setup(negedge TE,posedge CLK,1.0,notifier);
// setup TE-LH CLK-LH
$setup(posedge TE,posedge CLK,1.0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module ICGTP_X4( TE, E, CLK, Q );
input CLK, E, TE;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
ICGTP_X4_func ICGTP_X4_behav_inst(.TE(TE),.E(E),.CLK(CLK),.Q(Q),.notifier(notifier));
`else
ICGTP_X4_func ICGTP_X4_inst(.TE(TE),.E(E),.CLK(CLK),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,E);
not MGM_G1(MGM_W1,TE);
and MGM_G2(ENABLE_NOT_E_AND_NOT_TE,MGM_W1,MGM_W0);
not MGM_G3(MGM_W2,E);
and MGM_G4(ENABLE_NOT_E_AND_TE,TE,MGM_W2);
not MGM_G5(MGM_W3,TE);
and MGM_G6(ENABLE_E_AND_NOT_TE,MGM_W3,E);
and MGM_G7(ENABLE_E_AND_TE,TE,E);
// spec_gates_end
specify
// specify_block_begin
if(E===1'b0 && TE===1'b1)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b0)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b1 && TE===1'b1)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
ifnone
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
if(E===1'b0 && TE===1'b0)
// comb arc CLK --> Q
(CLK => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_E_AND_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_E_AND_NOT_TE === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_E_AND_TE === 1'b1)
,1.0,0,notifier);
// hold E-HL CLK-LH
$hold(posedge CLK,negedge E,1.0,notifier);
// hold E-LH CLK-LH
$hold(posedge CLK,posedge E,1.0,notifier);
// setup E-HL CLK-LH
$setup(negedge E,posedge CLK,1.0,notifier);
// setup E-LH CLK-LH
$setup(posedge E,posedge CLK,1.0,notifier);
// hold TE-HL CLK-LH
$hold(posedge CLK,negedge TE,1.0,notifier);
// hold TE-LH CLK-LH
$hold(posedge CLK,posedge TE,1.0,notifier);
// setup TE-HL CLK-LH
$setup(negedge TE,posedge CLK,1.0,notifier);
// setup TE-LH CLK-LH
$setup(posedge TE,posedge CLK,1.0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INVZ_X1( EN, ZN, I );
input EN, I;
output ZN;
`ifdef FUNCTIONAL // functional //
INVZ_X1_func INVZ_X1_behav_inst(.EN(EN),.ZN(ZN),.I(I));
`else
INVZ_X1_func INVZ_X1_inst(.EN(EN),.ZN(ZN),.I(I));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> ZN
(EN => ZN) = (1.0,1.0);
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INVZ_X12( EN, I, ZN );
input EN, I;
output ZN;
`ifdef FUNCTIONAL // functional //
INVZ_X12_func INVZ_X12_behav_inst(.EN(EN),.I(I),.ZN(ZN));
`else
INVZ_X12_func INVZ_X12_inst(.EN(EN),.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> ZN
(EN => ZN) = (1.0,1.0);
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INVZ_X16( EN, I, ZN );
input EN, I;
output ZN;
`ifdef FUNCTIONAL // functional //
INVZ_X16_func INVZ_X16_behav_inst(.EN(EN),.I(I),.ZN(ZN));
`else
INVZ_X16_func INVZ_X16_inst(.EN(EN),.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> ZN
(EN => ZN) = (1.0,1.0);
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INVZ_X2( EN, ZN, I );
input EN, I;
output ZN;
`ifdef FUNCTIONAL // functional //
INVZ_X2_func INVZ_X2_behav_inst(.EN(EN),.ZN(ZN),.I(I));
`else
INVZ_X2_func INVZ_X2_inst(.EN(EN),.ZN(ZN),.I(I));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> ZN
(EN => ZN) = (1.0,1.0);
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INVZ_X3( EN, I, ZN );
input EN, I;
output ZN;
`ifdef FUNCTIONAL // functional //
INVZ_X3_func INVZ_X3_behav_inst(.EN(EN),.I(I),.ZN(ZN));
`else
INVZ_X3_func INVZ_X3_inst(.EN(EN),.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> ZN
(EN => ZN) = (1.0,1.0);
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INVZ_X4( EN, I, ZN );
input EN, I;
output ZN;
`ifdef FUNCTIONAL // functional //
INVZ_X4_func INVZ_X4_behav_inst(.EN(EN),.I(I),.ZN(ZN));
`else
INVZ_X4_func INVZ_X4_inst(.EN(EN),.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> ZN
(EN => ZN) = (1.0,1.0);
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INVZ_X8( EN, I, ZN );
input EN, I;
output ZN;
`ifdef FUNCTIONAL // functional //
INVZ_X8_func INVZ_X8_behav_inst(.EN(EN),.I(I),.ZN(ZN));
`else
INVZ_X8_func INVZ_X8_inst(.EN(EN),.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc EN --> ZN
(EN => ZN) = (1.0,1.0);
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INV_X1( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
INV_X1_func INV_X1_behav_inst(.I(I),.ZN(ZN));
`else
INV_X1_func INV_X1_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INV_X12( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
INV_X12_func INV_X12_behav_inst(.I(I),.ZN(ZN));
`else
INV_X12_func INV_X12_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INV_X16( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
INV_X16_func INV_X16_behav_inst(.I(I),.ZN(ZN));
`else
INV_X16_func INV_X16_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INV_X2( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
INV_X2_func INV_X2_behav_inst(.I(I),.ZN(ZN));
`else
INV_X2_func INV_X2_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INV_X20( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
INV_X20_func INV_X20_behav_inst(.I(I),.ZN(ZN));
`else
INV_X20_func INV_X20_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INV_X3( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
INV_X3_func INV_X3_behav_inst(.I(I),.ZN(ZN));
`else
INV_X3_func INV_X3_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INV_X4( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
INV_X4_func INV_X4_behav_inst(.I(I),.ZN(ZN));
`else
INV_X4_func INV_X4_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module INV_X8( I, ZN );
input I;
output ZN;
`ifdef FUNCTIONAL // functional //
INV_X8_func INV_X8_behav_inst(.I(I),.ZN(ZN));
`else
INV_X8_func INV_X8_inst(.I(I),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc I --> ZN
(I => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATQ_X1( E, D, Q );
input D, E;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATQ_X1_func LATQ_X1_behav_inst(.E(E),.D(D),.Q(Q),.notifier(notifier));
`else
LATQ_X1_func LATQ_X1_inst(.E(E),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E,negedge D,1.0,notifier);
// hold D-LH E-HL
$hold(negedge E,posedge D,1.0,notifier);
// setup D-HL E-HL
$setup(negedge D,negedge E,1.0,notifier);
// setup D-LH E-HL
$setup(posedge D,negedge E,1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATQ_X2( E, D, Q );
input D, E;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATQ_X2_func LATQ_X2_behav_inst(.E(E),.D(D),.Q(Q),.notifier(notifier));
`else
LATQ_X2_func LATQ_X2_inst(.E(E),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E,negedge D,1.0,notifier);
// hold D-LH E-HL
$hold(negedge E,posedge D,1.0,notifier);
// setup D-HL E-HL
$setup(negedge D,negedge E,1.0,notifier);
// setup D-LH E-HL
$setup(posedge D,negedge E,1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATQ_X4( E, D, Q );
input D, E;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATQ_X4_func LATQ_X4_behav_inst(.E(E),.D(D),.Q(Q),.notifier(notifier));
`else
LATQ_X4_func LATQ_X4_inst(.E(E),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(ENABLE_NOT_D,D);
buf MGM_G1(ENABLE_D,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E,negedge D,1.0,notifier);
// hold D-LH E-HL
$hold(negedge E,posedge D,1.0,notifier);
// setup D-HL E-HL
$setup(negedge D,negedge E,1.0,notifier);
// setup D-LH E-HL
$setup(posedge D,negedge E,1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATRNQ_X1( E, RN, D, Q );
input D, E, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATRNQ_X1_func LATRNQ_X1_behav_inst(.E(E),.RN(RN),.D(D),.Q(Q),.notifier(notifier));
`else
LATRNQ_X1_func LATRNQ_X1_inst(.E(E),.RN(RN),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
buf MGM_G0(ENABLE_RN,RN);
not MGM_G1(MGM_W0,D);
and MGM_G2(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G3(ENABLE_D_AND_RN,RN,D);
not MGM_G4(MGM_W1,D);
not MGM_G5(MGM_W2,E);
and MGM_G6(ENABLE_NOT_D_AND_NOT_E,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,E);
and MGM_G8(ENABLE_D_AND_NOT_E,MGM_W3,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// recovery RN-LH E-HL
$recovery(posedge RN,negedge E,1.0,notifier);
// removal RN-LH E-HL
$removal(posedge RN,negedge E,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATRNQ_X2( E, RN, D, Q );
input D, E, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATRNQ_X2_func LATRNQ_X2_behav_inst(.E(E),.RN(RN),.D(D),.Q(Q),.notifier(notifier));
`else
LATRNQ_X2_func LATRNQ_X2_inst(.E(E),.RN(RN),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
buf MGM_G0(ENABLE_RN,RN);
not MGM_G1(MGM_W0,D);
and MGM_G2(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G3(ENABLE_D_AND_RN,RN,D);
not MGM_G4(MGM_W1,D);
not MGM_G5(MGM_W2,E);
and MGM_G6(ENABLE_NOT_D_AND_NOT_E,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,E);
and MGM_G8(ENABLE_D_AND_NOT_E,MGM_W3,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// recovery RN-LH E-HL
$recovery(posedge RN,negedge E,1.0,notifier);
// removal RN-LH E-HL
$removal(posedge RN,negedge E,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATRNQ_X4( E, RN, D, Q );
input D, E, RN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATRNQ_X4_func LATRNQ_X4_behav_inst(.E(E),.RN(RN),.D(D),.Q(Q),.notifier(notifier));
`else
LATRNQ_X4_func LATRNQ_X4_inst(.E(E),.RN(RN),.D(D),.Q(Q),.notifier(notifier));
// spec_gates_begin
buf MGM_G0(ENABLE_RN,RN);
not MGM_G1(MGM_W0,D);
and MGM_G2(ENABLE_NOT_D_AND_RN,RN,MGM_W0);
and MGM_G3(ENABLE_D_AND_RN,RN,D);
not MGM_G4(MGM_W1,D);
not MGM_G5(MGM_W2,E);
and MGM_G6(ENABLE_NOT_D_AND_NOT_E,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,E);
and MGM_G8(ENABLE_D_AND_NOT_E,MGM_W3,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_RN === 1'b1),
negedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_RN === 1'b1),
posedge D &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_RN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_RN === 1'b1)
,1.0,0,notifier);
// recovery RN-LH E-HL
$recovery(posedge RN,negedge E,1.0,notifier);
// removal RN-LH E-HL
$removal(posedge RN,negedge E,1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATRSNQ_X1( E, RN, D, SETN, Q );
input D, E, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATRSNQ_X1_func LATRSNQ_X1_behav_inst(.E(E),.RN(RN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
LATRSNQ_X1_func LATRSNQ_X1_inst(.E(E),.RN(RN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
and MGM_G0(ENABLE_RN_AND_SETN,SETN,RN);
not MGM_G1(MGM_W0,D);
and MGM_G2(MGM_W1,RN,MGM_W0);
and MGM_G3(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G4(MGM_W2,RN,D);
and MGM_G5(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,D);
not MGM_G8(MGM_W4,E);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_D_AND_NOT_E_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,E);
and MGM_G12(MGM_W7,MGM_W6,D);
and MGM_G13(ENABLE_D_AND_NOT_E_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
not MGM_G15(MGM_W9,E);
and MGM_G16(ENABLE_NOT_D_AND_NOT_E,MGM_W9,MGM_W8);
not MGM_G17(MGM_W10,E);
and MGM_G18(ENABLE_D_AND_NOT_E,MGM_W10,D);
buf MGM_G19(ENABLE_RN,RN);
not MGM_G20(MGM_W11,D);
not MGM_G21(MGM_W12,E);
and MGM_G22(MGM_W13,MGM_W12,MGM_W11);
and MGM_G23(ENABLE_NOT_D_AND_NOT_E_AND_RN,RN,MGM_W13);
not MGM_G24(MGM_W14,E);
and MGM_G25(MGM_W15,MGM_W14,D);
and MGM_G26(ENABLE_D_AND_NOT_E_AND_RN,RN,MGM_W15);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b0 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b0 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// recovery RN-LH E-HL
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH E-HL
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_D_AND_NOT_E_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_D_AND_NOT_E_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// recovery SETN-LH E-HL
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH E-HL
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_D_AND_NOT_E_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_D_AND_NOT_E_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATRSNQ_X2( E, RN, D, SETN, Q );
input D, E, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATRSNQ_X2_func LATRSNQ_X2_behav_inst(.E(E),.RN(RN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
LATRSNQ_X2_func LATRSNQ_X2_inst(.E(E),.RN(RN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
and MGM_G0(ENABLE_RN_AND_SETN,SETN,RN);
not MGM_G1(MGM_W0,D);
and MGM_G2(MGM_W1,RN,MGM_W0);
and MGM_G3(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G4(MGM_W2,RN,D);
and MGM_G5(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,D);
not MGM_G8(MGM_W4,E);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_D_AND_NOT_E_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,E);
and MGM_G12(MGM_W7,MGM_W6,D);
and MGM_G13(ENABLE_D_AND_NOT_E_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
not MGM_G15(MGM_W9,E);
and MGM_G16(ENABLE_NOT_D_AND_NOT_E,MGM_W9,MGM_W8);
not MGM_G17(MGM_W10,E);
and MGM_G18(ENABLE_D_AND_NOT_E,MGM_W10,D);
buf MGM_G19(ENABLE_RN,RN);
not MGM_G20(MGM_W11,D);
not MGM_G21(MGM_W12,E);
and MGM_G22(MGM_W13,MGM_W12,MGM_W11);
and MGM_G23(ENABLE_NOT_D_AND_NOT_E_AND_RN,RN,MGM_W13);
not MGM_G24(MGM_W14,E);
and MGM_G25(MGM_W15,MGM_W14,D);
and MGM_G26(ENABLE_D_AND_NOT_E_AND_RN,RN,MGM_W15);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b0 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b0 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// recovery RN-LH E-HL
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH E-HL
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_D_AND_NOT_E_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_D_AND_NOT_E_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// recovery SETN-LH E-HL
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH E-HL
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_D_AND_NOT_E_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_D_AND_NOT_E_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATRSNQ_X4( E, RN, D, SETN, Q );
input D, E, RN, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATRSNQ_X4_func LATRSNQ_X4_behav_inst(.E(E),.RN(RN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
LATRSNQ_X4_func LATRSNQ_X4_inst(.E(E),.RN(RN),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
and MGM_G0(ENABLE_RN_AND_SETN,SETN,RN);
not MGM_G1(MGM_W0,D);
and MGM_G2(MGM_W1,RN,MGM_W0);
and MGM_G3(ENABLE_NOT_D_AND_RN_AND_SETN,SETN,MGM_W1);
and MGM_G4(MGM_W2,RN,D);
and MGM_G5(ENABLE_D_AND_RN_AND_SETN,SETN,MGM_W2);
buf MGM_G6(ENABLE_SETN,SETN);
not MGM_G7(MGM_W3,D);
not MGM_G8(MGM_W4,E);
and MGM_G9(MGM_W5,MGM_W4,MGM_W3);
and MGM_G10(ENABLE_NOT_D_AND_NOT_E_AND_SETN,SETN,MGM_W5);
not MGM_G11(MGM_W6,E);
and MGM_G12(MGM_W7,MGM_W6,D);
and MGM_G13(ENABLE_D_AND_NOT_E_AND_SETN,SETN,MGM_W7);
not MGM_G14(MGM_W8,D);
not MGM_G15(MGM_W9,E);
and MGM_G16(ENABLE_NOT_D_AND_NOT_E,MGM_W9,MGM_W8);
not MGM_G17(MGM_W10,E);
and MGM_G18(ENABLE_D_AND_NOT_E,MGM_W10,D);
buf MGM_G19(ENABLE_RN,RN);
not MGM_G20(MGM_W11,D);
not MGM_G21(MGM_W12,E);
and MGM_G22(MGM_W13,MGM_W12,MGM_W11);
and MGM_G23(ENABLE_NOT_D_AND_NOT_E_AND_RN,RN,MGM_W13);
not MGM_G24(MGM_W14,E);
and MGM_G25(MGM_W15,MGM_W14,D);
and MGM_G26(ENABLE_D_AND_NOT_E_AND_RN,RN,MGM_W15);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b0 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b1 && RN===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b0 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0 && RN===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),
posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_RN_AND_SETN === 1'b1),
negedge E &&& (ENABLE_RN_AND_SETN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_RN_AND_SETN === 1'b1)
,1.0,0,notifier);
// recovery RN-LH E-HL
$recovery(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// removal RN-LH E-HL
$removal(posedge RN &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_D_AND_NOT_E_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_D_AND_NOT_E_AND_SETN === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// recovery SETN-LH E-HL
$recovery(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// removal SETN-LH E-HL
$removal(posedge SETN &&& (ENABLE_RN === 1'b1),
negedge E &&& (ENABLE_RN === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1),
posedge RN &&& (ENABLE_D_AND_NOT_E === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_D_AND_NOT_E_AND_RN === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_D_AND_NOT_E_AND_RN === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATSNQ_X1( E, D, SETN, Q );
input D, E, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATSNQ_X1_func LATSNQ_X1_behav_inst(.E(E),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
LATSNQ_X1_func LATSNQ_X1_inst(.E(E),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
buf MGM_G0(ENABLE_SETN,SETN);
not MGM_G1(MGM_W0,D);
and MGM_G2(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G3(ENABLE_D_AND_SETN,SETN,D);
not MGM_G4(MGM_W1,D);
not MGM_G5(MGM_W2,E);
and MGM_G6(ENABLE_NOT_D_AND_NOT_E,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,E);
and MGM_G8(ENABLE_D_AND_NOT_E,MGM_W3,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// recovery SETN-LH E-HL
$recovery(posedge SETN,negedge E,1.0,notifier);
// removal SETN-LH E-HL
$removal(posedge SETN,negedge E,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATSNQ_X2( E, D, SETN, Q );
input D, E, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATSNQ_X2_func LATSNQ_X2_behav_inst(.E(E),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
LATSNQ_X2_func LATSNQ_X2_inst(.E(E),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
buf MGM_G0(ENABLE_SETN,SETN);
not MGM_G1(MGM_W0,D);
and MGM_G2(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G3(ENABLE_D_AND_SETN,SETN,D);
not MGM_G4(MGM_W1,D);
not MGM_G5(MGM_W2,E);
and MGM_G6(ENABLE_NOT_D_AND_NOT_E,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,E);
and MGM_G8(ENABLE_D_AND_NOT_E,MGM_W3,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// recovery SETN-LH E-HL
$recovery(posedge SETN,negedge E,1.0,notifier);
// removal SETN-LH E-HL
$removal(posedge SETN,negedge E,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module LATSNQ_X4( E, D, SETN, Q );
input D, E, SETN;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
LATSNQ_X4_func LATSNQ_X4_behav_inst(.E(E),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
LATSNQ_X4_func LATSNQ_X4_inst(.E(E),.D(D),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
buf MGM_G0(ENABLE_SETN,SETN);
not MGM_G1(MGM_W0,D);
and MGM_G2(ENABLE_NOT_D_AND_SETN,SETN,MGM_W0);
and MGM_G3(ENABLE_D_AND_SETN,SETN,D);
not MGM_G4(MGM_W1,D);
not MGM_G5(MGM_W2,E);
and MGM_G6(ENABLE_NOT_D_AND_NOT_E,MGM_W2,MGM_W1);
not MGM_G7(MGM_W3,E);
and MGM_G8(ENABLE_D_AND_NOT_E,MGM_W3,D);
// spec_gates_end
specify
// specify_block_begin
// comb arc D --> Q
(D => Q) = (1.0,1.0);
// seq arc E --> Q
(posedge E => (Q : D)) = (1.0,1.0);
if(D===1'b0 && E===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b0 && E===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(D===1'b1 && E===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
// hold D-HL E-HL
$hold(negedge E &&& (ENABLE_SETN === 1'b1),
negedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// hold D-LH E-HL
$hold(negedge E &&& (ENABLE_SETN === 1'b1),
posedge D &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-HL E-HL
$setup(negedge D &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
// setup D-LH E-HL
$setup(posedge D &&& (ENABLE_SETN === 1'b1),
negedge E &&& (ENABLE_SETN === 1'b1),1.0,notifier);
$width(posedge E &&& (ENABLE_NOT_D_AND_SETN === 1'b1)
,1.0,0,notifier);
$width(posedge E &&& (ENABLE_D_AND_SETN === 1'b1)
,1.0,0,notifier);
// recovery SETN-LH E-HL
$recovery(posedge SETN,negedge E,1.0,notifier);
// removal SETN-LH E-HL
$removal(posedge SETN,negedge E,1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_D_AND_NOT_E === 1'b1)
,1.0,0,notifier);
// mpw E_lh
$width(posedge E,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module MUX2_X1( Z, I1, S, I0 );
input I0, I1, S;
output Z;
`ifdef FUNCTIONAL // functional //
MUX2_X1_func MUX2_X1_behav_inst(.Z(Z),.I1(I1),.S(S),.I0(I0));
`else
MUX2_X1_func MUX2_X1_inst(.Z(Z),.I1(I1),.S(S),.I0(I0));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(I1===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
ifnone
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I0===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S --> (Z:S)
(posedge S => (Z:S)) = (1.0,1.0);
ifnone
// comb arc negedge S --> (Z:S)
(negedge S => (Z:S)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module MUX2_X2( Z, I1, S, I0 );
input I0, I1, S;
output Z;
`ifdef FUNCTIONAL // functional //
MUX2_X2_func MUX2_X2_behav_inst(.Z(Z),.I1(I1),.S(S),.I0(I0));
`else
MUX2_X2_func MUX2_X2_inst(.Z(Z),.I1(I1),.S(S),.I0(I0));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(I1===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
ifnone
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I0===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S --> (Z:S)
(posedge S => (Z:S)) = (1.0,1.0);
ifnone
// comb arc negedge S --> (Z:S)
(negedge S => (Z:S)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module MUX2_X4( Z, I1, S, I0 );
input I0, I1, S;
output Z;
`ifdef FUNCTIONAL // functional //
MUX2_X4_func MUX2_X4_behav_inst(.Z(Z),.I1(I1),.S(S),.I0(I0));
`else
MUX2_X4_func MUX2_X4_inst(.Z(Z),.I1(I1),.S(S),.I0(I0));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(I1===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
ifnone
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I0===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S --> (Z:S)
(posedge S => (Z:S)) = (1.0,1.0);
ifnone
// comb arc negedge S --> (Z:S)
(negedge S => (Z:S)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module MUX4_X1( I2, S0, I3, Z, S1, I1, I0 );
input I0, I1, I2, I3, S0, S1;
output Z;
`ifdef FUNCTIONAL // functional //
MUX4_X1_func MUX4_X1_behav_inst(.I2(I2),.S0(S0),.I3(I3),.Z(Z),.S1(S1),.I1(I1),.I0(I0));
`else
MUX4_X1_func MUX4_X1_inst(.I2(I2),.S0(S0),.I3(I3),.Z(Z),.S1(S1),.I1(I1),.I0(I0));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(I1===1'b0 && I2===1'b0 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b0 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b1 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b1 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b0 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b0 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b1 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b1 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
ifnone
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b0 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b0 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b1 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b1 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b0 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b0 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b1 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b1 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
ifnone
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
ifnone
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S0 --> (Z:S0)
(posedge S0 => (Z:S0)) = (1.0,1.0);
ifnone
// comb arc negedge S0 --> (Z:S0)
(negedge S0 => (Z:S0)) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S1 --> (Z:S1)
(posedge S1 => (Z:S1)) = (1.0,1.0);
ifnone
// comb arc negedge S1 --> (Z:S1)
(negedge S1 => (Z:S1)) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module MUX4_X2( I2, S0, I3, Z, S1, I1, I0 );
input I0, I1, I2, I3, S0, S1;
output Z;
`ifdef FUNCTIONAL // functional //
MUX4_X2_func MUX4_X2_behav_inst(.I2(I2),.S0(S0),.I3(I3),.Z(Z),.S1(S1),.I1(I1),.I0(I0));
`else
MUX4_X2_func MUX4_X2_inst(.I2(I2),.S0(S0),.I3(I3),.Z(Z),.S1(S1),.I1(I1),.I0(I0));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(I1===1'b0 && I2===1'b0 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b0 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b1 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b1 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b0 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b0 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b1 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b1 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
ifnone
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b0 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b0 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b1 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b1 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b0 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b0 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b1 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b1 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
ifnone
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
ifnone
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S0 --> (Z:S0)
(posedge S0 => (Z:S0)) = (1.0,1.0);
ifnone
// comb arc negedge S0 --> (Z:S0)
(negedge S0 => (Z:S0)) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S1 --> (Z:S1)
(posedge S1 => (Z:S1)) = (1.0,1.0);
ifnone
// comb arc negedge S1 --> (Z:S1)
(negedge S1 => (Z:S1)) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module MUX4_X4( I2, S0, I3, Z, S1, I1, I0 );
input I0, I1, I2, I3, S0, S1;
output Z;
`ifdef FUNCTIONAL // functional //
MUX4_X4_func MUX4_X4_behav_inst(.I2(I2),.S0(S0),.I3(I3),.Z(Z),.S1(S1),.I1(I1),.I0(I0));
`else
MUX4_X4_func MUX4_X4_inst(.I2(I2),.S0(S0),.I3(I3),.Z(Z),.S1(S1),.I1(I1),.I0(I0));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(I1===1'b0 && I2===1'b0 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b0 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b1 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b0 && I2===1'b1 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b0 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b0 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b1 && I3===1'b0)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I1===1'b1 && I2===1'b1 && I3===1'b1)
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
ifnone
// comb arc I0 --> Z
(I0 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b0 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b0 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b1 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I2===1'b1 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b0 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b0 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b1 && I3===1'b0)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b1 && I2===1'b1 && I3===1'b1)
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
ifnone
// comb arc I1 --> Z
(I1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I3===1'b0)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I3===1'b1)
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
ifnone
// comb arc I2 --> Z
(I2 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1)
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
ifnone
// comb arc I3 --> Z
(I3 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S0 --> (Z:S0)
(posedge S0 => (Z:S0)) = (1.0,1.0);
ifnone
// comb arc negedge S0 --> (Z:S0)
(negedge S0 => (Z:S0)) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b1 && S1===1'b0)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S1===1'b1)
// comb arc S0 --> Z
(S0 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b0 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge S1 --> (Z:S1)
(posedge S1 => (Z:S1)) = (1.0,1.0);
ifnone
// comb arc negedge S1 --> (Z:S1)
(negedge S1 => (Z:S1)) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b0 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b0 && I1===1'b1 && I2===1'b1 && I3===1'b1 && S0===1'b0)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b0 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
if(I0===1'b1 && I1===1'b0 && I2===1'b1 && I3===1'b1 && S0===1'b1)
// comb arc S1 --> Z
(S1 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND2_X1( A2, ZN, A1 );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND2_X1_func NAND2_X1_behav_inst(.A2(A2),.ZN(ZN),.A1(A1));
`else
NAND2_X1_func NAND2_X1_inst(.A2(A2),.ZN(ZN),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND2_X2( A2, ZN, A1 );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND2_X2_func NAND2_X2_behav_inst(.A2(A2),.ZN(ZN),.A1(A1));
`else
NAND2_X2_func NAND2_X2_inst(.A2(A2),.ZN(ZN),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND2_X4( A2, ZN, A1 );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND2_X4_func NAND2_X4_behav_inst(.A2(A2),.ZN(ZN),.A1(A1));
`else
NAND2_X4_func NAND2_X4_inst(.A2(A2),.ZN(ZN),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND3_X1( A3, ZN, A2, A1 );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND3_X1_func NAND3_X1_behav_inst(.A3(A3),.ZN(ZN),.A2(A2),.A1(A1));
`else
NAND3_X1_func NAND3_X1_inst(.A3(A3),.ZN(ZN),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND3_X2( ZN, A3, A2, A1 );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND3_X2_func NAND3_X2_behav_inst(.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
`else
NAND3_X2_func NAND3_X2_inst(.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND3_X4( A2, A3, ZN, A1 );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND3_X4_func NAND3_X4_behav_inst(.A2(A2),.A3(A3),.ZN(ZN),.A1(A1));
`else
NAND3_X4_func NAND3_X4_inst(.A2(A2),.A3(A3),.ZN(ZN),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND4_X1( A4, ZN, A3, A2, A1 );
input A1, A2, A3, A4;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND4_X1_func NAND4_X1_behav_inst(.A4(A4),.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
`else
NAND4_X1_func NAND4_X1_inst(.A4(A4),.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// comb arc A4 --> ZN
(A4 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND4_X2( ZN, A4, A3, A2, A1 );
input A1, A2, A3, A4;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND4_X2_func NAND4_X2_behav_inst(.ZN(ZN),.A4(A4),.A3(A3),.A2(A2),.A1(A1));
`else
NAND4_X2_func NAND4_X2_inst(.ZN(ZN),.A4(A4),.A3(A3),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// comb arc A4 --> ZN
(A4 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NAND4_X4( A3, ZN, A4, A2, A1 );
input A1, A2, A3, A4;
output ZN;
`ifdef FUNCTIONAL // functional //
NAND4_X4_func NAND4_X4_behav_inst(.A3(A3),.ZN(ZN),.A4(A4),.A2(A2),.A1(A1));
`else
NAND4_X4_func NAND4_X4_inst(.A3(A3),.ZN(ZN),.A4(A4),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// comb arc A4 --> ZN
(A4 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR2_X1( A2, ZN, A1 );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR2_X1_func NOR2_X1_behav_inst(.A2(A2),.ZN(ZN),.A1(A1));
`else
NOR2_X1_func NOR2_X1_inst(.A2(A2),.ZN(ZN),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR2_X2( A2, ZN, A1 );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR2_X2_func NOR2_X2_behav_inst(.A2(A2),.ZN(ZN),.A1(A1));
`else
NOR2_X2_func NOR2_X2_inst(.A2(A2),.ZN(ZN),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR2_X4( ZN, A2, A1 );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR2_X4_func NOR2_X4_behav_inst(.ZN(ZN),.A2(A2),.A1(A1));
`else
NOR2_X4_func NOR2_X4_inst(.ZN(ZN),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR3_X1( A3, ZN, A2, A1 );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR3_X1_func NOR3_X1_behav_inst(.A3(A3),.ZN(ZN),.A2(A2),.A1(A1));
`else
NOR3_X1_func NOR3_X1_inst(.A3(A3),.ZN(ZN),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR3_X2( ZN, A3, A2, A1 );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR3_X2_func NOR3_X2_behav_inst(.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
`else
NOR3_X2_func NOR3_X2_inst(.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR3_X4( A2, ZN, A3, A1 );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR3_X4_func NOR3_X4_behav_inst(.A2(A2),.ZN(ZN),.A3(A3),.A1(A1));
`else
NOR3_X4_func NOR3_X4_inst(.A2(A2),.ZN(ZN),.A3(A3),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR4_X1( A4, ZN, A3, A2, A1 );
input A1, A2, A3, A4;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR4_X1_func NOR4_X1_behav_inst(.A4(A4),.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
`else
NOR4_X1_func NOR4_X1_inst(.A4(A4),.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// comb arc A4 --> ZN
(A4 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR4_X2( A3, ZN, A4, A2, A1 );
input A1, A2, A3, A4;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR4_X2_func NOR4_X2_behav_inst(.A3(A3),.ZN(ZN),.A4(A4),.A2(A2),.A1(A1));
`else
NOR4_X2_func NOR4_X2_inst(.A3(A3),.ZN(ZN),.A4(A4),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// comb arc A4 --> ZN
(A4 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module NOR4_X4( A3, ZN, A4, A2, A1 );
input A1, A2, A3, A4;
output ZN;
`ifdef FUNCTIONAL // functional //
NOR4_X4_func NOR4_X4_behav_inst(.A3(A3),.ZN(ZN),.A4(A4),.A2(A2),.A1(A1));
`else
NOR4_X4_func NOR4_X4_inst(.A3(A3),.ZN(ZN),.A4(A4),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// comb arc A4 --> ZN
(A4 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI211_X1( A2, ZN, A1, B, C );
input A1, A2, B, C;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI211_X1_func OAI211_X1_behav_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B),.C(C));
`else
OAI211_X1_func OAI211_X1_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B),.C(C));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI211_X2( ZN, A2, A1, B, C );
input A1, A2, B, C;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI211_X2_func OAI211_X2_behav_inst(.ZN(ZN),.A2(A2),.A1(A1),.B(B),.C(C));
`else
OAI211_X2_func OAI211_X2_inst(.ZN(ZN),.A2(A2),.A1(A1),.B(B),.C(C));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI211_X4( ZN, A2, A1, B, C );
input A1, A2, B, C;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI211_X4_func OAI211_X4_behav_inst(.ZN(ZN),.A2(A2),.A1(A1),.B(B),.C(C));
`else
OAI211_X4_func OAI211_X4_inst(.ZN(ZN),.A2(A2),.A1(A1),.B(B),.C(C));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI21_X1( A2, ZN, A1, B );
input A1, A2, B;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI21_X1_func OAI21_X1_behav_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B));
`else
OAI21_X1_func OAI21_X1_inst(.A2(A2),.ZN(ZN),.A1(A1),.B(B));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI21_X2( B, ZN, A2, A1 );
input A1, A2, B;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI21_X2_func OAI21_X2_behav_inst(.B(B),.ZN(ZN),.A2(A2),.A1(A1));
`else
OAI21_X2_func OAI21_X2_inst(.B(B),.ZN(ZN),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI21_X4( ZN, A2, A1, B );
input A1, A2, B;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI21_X4_func OAI21_X4_behav_inst(.ZN(ZN),.A2(A2),.A1(A1),.B(B));
`else
OAI21_X4_func OAI21_X4_inst(.ZN(ZN),.A2(A2),.A1(A1),.B(B));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI221_X1( B2, B1, ZN, C, A2, A1 );
input A1, A2, B1, B2, C;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI221_X1_func OAI221_X1_behav_inst(.B2(B2),.B1(B1),.ZN(ZN),.C(C),.A2(A2),.A1(A1));
`else
OAI221_X1_func OAI221_X1_inst(.B2(B2),.B1(B1),.ZN(ZN),.C(C),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI221_X2( ZN, C, B2, B1, A1, A2 );
input A1, A2, B1, B2, C;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI221_X2_func OAI221_X2_behav_inst(.ZN(ZN),.C(C),.B2(B2),.B1(B1),.A1(A1),.A2(A2));
`else
OAI221_X2_func OAI221_X2_inst(.ZN(ZN),.C(C),.B2(B2),.B1(B1),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI221_X4( ZN, B1, B2, C, A1, A2 );
input A1, A2, B1, B2, C;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI221_X4_func OAI221_X4_behav_inst(.ZN(ZN),.B1(B1),.B2(B2),.C(C),.A1(A1),.A2(A2));
`else
OAI221_X4_func OAI221_X4_inst(.ZN(ZN),.B1(B1),.B2(B2),.C(C),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
ifnone
// comb arc C --> ZN
(C => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI222_X1( C2, C1, ZN, B1, B2, A2, A1 );
input A1, A2, B1, B2, C1, C2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI222_X1_func OAI222_X1_behav_inst(.C2(C2),.C1(C1),.ZN(ZN),.B1(B1),.B2(B2),.A2(A2),.A1(A1));
`else
OAI222_X1_func OAI222_X1_inst(.C2(C2),.C1(C1),.ZN(ZN),.B1(B1),.B2(B2),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
ifnone
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
ifnone
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI222_X2( ZN, C1, C2, B1, B2, A1, A2 );
input A1, A2, B1, B2, C1, C2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI222_X2_func OAI222_X2_behav_inst(.ZN(ZN),.C1(C1),.C2(C2),.B1(B1),.B2(B2),.A1(A1),.A2(A2));
`else
OAI222_X2_func OAI222_X2_inst(.ZN(ZN),.C1(C1),.C2(C2),.B1(B1),.B2(B2),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
ifnone
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
ifnone
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI222_X4( ZN, C1, C2, B1, B2, A1, A2 );
input A1, A2, B1, B2, C1, C2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI222_X4_func OAI222_X4_behav_inst(.ZN(ZN),.C1(C1),.C2(C2),.B1(B1),.B2(B2),.A1(A1),.A2(A2));
`else
OAI222_X4_func OAI222_X4_inst(.ZN(ZN),.C1(C1),.C2(C2),.B1(B1),.B2(B2),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b0 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && C1===1'b1 && C2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
ifnone
// comb arc C1 --> ZN
(C1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b0 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b0)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && B1===1'b1 && B2===1'b1)
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
ifnone
// comb arc C2 --> ZN
(C2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI22_X1( B2, B1, ZN, A1, A2 );
input A1, A2, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI22_X1_func OAI22_X1_behav_inst(.B2(B2),.B1(B1),.ZN(ZN),.A1(A1),.A2(A2));
`else
OAI22_X1_func OAI22_X1_inst(.B2(B2),.B1(B1),.ZN(ZN),.A1(A1),.A2(A2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI22_X2( B2, B1, ZN, A2, A1 );
input A1, A2, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI22_X2_func OAI22_X2_behav_inst(.B2(B2),.B1(B1),.ZN(ZN),.A2(A2),.A1(A1));
`else
OAI22_X2_func OAI22_X2_inst(.B2(B2),.B1(B1),.ZN(ZN),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI22_X4( B2, ZN, B1, A2, A1 );
input A1, A2, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI22_X4_func OAI22_X4_behav_inst(.B2(B2),.ZN(ZN),.B1(B1),.A2(A2),.A1(A1));
`else
OAI22_X4_func OAI22_X4_inst(.B2(B2),.ZN(ZN),.B1(B1),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI31_X1( B, ZN, A1, A2, A3 );
input A1, A2, A3, B;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI31_X1_func OAI31_X1_behav_inst(.B(B),.ZN(ZN),.A1(A1),.A2(A2),.A3(A3));
`else
OAI31_X1_func OAI31_X1_inst(.B(B),.ZN(ZN),.A1(A1),.A2(A2),.A3(A3));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI31_X2( B, ZN, A3, A2, A1 );
input A1, A2, A3, B;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI31_X2_func OAI31_X2_behav_inst(.B(B),.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
`else
OAI31_X2_func OAI31_X2_inst(.B(B),.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI31_X4( A3, ZN, A2, A1, B );
input A1, A2, A3, B;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI31_X4_func OAI31_X4_behav_inst(.A3(A3),.ZN(ZN),.A2(A2),.A1(A1),.B(B));
`else
OAI31_X4_func OAI31_X4_inst(.A3(A3),.ZN(ZN),.A2(A2),.A1(A1),.B(B));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
ifnone
// comb arc B --> ZN
(B => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI32_X1( A3, A2, A1, ZN, B1, B2 );
input A1, A2, A3, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI32_X1_func OAI32_X1_behav_inst(.A3(A3),.A2(A2),.A1(A1),.ZN(ZN),.B1(B1),.B2(B2));
`else
OAI32_X1_func OAI32_X1_inst(.A3(A3),.A2(A2),.A1(A1),.ZN(ZN),.B1(B1),.B2(B2));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI32_X2( A3, A2, A1, ZN, B2, B1 );
input A1, A2, A3, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI32_X2_func OAI32_X2_behav_inst(.A3(A3),.A2(A2),.A1(A1),.ZN(ZN),.B2(B2),.B1(B1));
`else
OAI32_X2_func OAI32_X2_inst(.A3(A3),.A2(A2),.A1(A1),.ZN(ZN),.B2(B2),.B1(B1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI32_X4( A2, A3, A1, ZN, B2, B1 );
input A1, A2, A3, B1, B2;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI32_X4_func OAI32_X4_behav_inst(.A2(A2),.A3(A3),.A1(A1),.ZN(ZN),.B2(B2),.B1(B1));
`else
OAI32_X4_func OAI32_X4_inst(.A2(A2),.A3(A3),.A1(A1),.ZN(ZN),.B2(B2),.B1(B1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI33_X1( B3, B2, B1, ZN, A1, A2, A3 );
input A1, A2, A3, B1, B2, B3;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI33_X1_func OAI33_X1_behav_inst(.B3(B3),.B2(B2),.B1(B1),.ZN(ZN),.A1(A1),.A2(A2),.A3(A3));
`else
OAI33_X1_func OAI33_X1_inst(.B3(B3),.B2(B2),.B1(B1),.ZN(ZN),.A1(A1),.A2(A2),.A3(A3));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
ifnone
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI33_X2( B3, B2, B1, ZN, A3, A2, A1 );
input A1, A2, A3, B1, B2, B3;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI33_X2_func OAI33_X2_behav_inst(.B3(B3),.B2(B2),.B1(B1),.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
`else
OAI33_X2_func OAI33_X2_inst(.B3(B3),.B2(B2),.B1(B1),.ZN(ZN),.A3(A3),.A2(A2),.A1(A1));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
ifnone
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OAI33_X4( B2, B3, B1, ZN, A1, A2, A3 );
input A1, A2, A3, B1, B2, B3;
output ZN;
`ifdef FUNCTIONAL // functional //
OAI33_X4_func OAI33_X4_behav_inst(.B2(B2),.B3(B3),.B1(B1),.ZN(ZN),.A1(A1),.A2(A2),.A3(A3));
`else
OAI33_X4_func OAI33_X4_inst(.B2(B2),.B3(B3),.B1(B1),.ZN(ZN),.A1(A1),.A2(A2),.A3(A3));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b0 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b0 && B2===1'b1 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b0 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(B1===1'b1 && B2===1'b1 && B3===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
ifnone
// comb arc B1 --> ZN
(B1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
ifnone
// comb arc B2 --> ZN
(B2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b0)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1 && A3===1'b1)
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
ifnone
// comb arc B3 --> ZN
(B3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR2_X1( A1, A2, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
OR2_X1_func OR2_X1_behav_inst(.A1(A1),.A2(A2),.Z(Z));
`else
OR2_X1_func OR2_X1_inst(.A1(A1),.A2(A2),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR2_X2( A1, A2, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
OR2_X2_func OR2_X2_behav_inst(.A1(A1),.A2(A2),.Z(Z));
`else
OR2_X2_func OR2_X2_inst(.A1(A1),.A2(A2),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR2_X4( A2, A1, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
OR2_X4_func OR2_X4_behav_inst(.A2(A2),.A1(A1),.Z(Z));
`else
OR2_X4_func OR2_X4_inst(.A2(A2),.A1(A1),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR3_X1( A1, A2, A3, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
OR3_X1_func OR3_X1_behav_inst(.A1(A1),.A2(A2),.A3(A3),.Z(Z));
`else
OR3_X1_func OR3_X1_inst(.A1(A1),.A2(A2),.A3(A3),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR3_X2( A1, A2, A3, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
OR3_X2_func OR3_X2_behav_inst(.A1(A1),.A2(A2),.A3(A3),.Z(Z));
`else
OR3_X2_func OR3_X2_inst(.A1(A1),.A2(A2),.A3(A3),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR3_X4( A3, A2, A1, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
OR3_X4_func OR3_X4_behav_inst(.A3(A3),.A2(A2),.A1(A1),.Z(Z));
`else
OR3_X4_func OR3_X4_inst(.A3(A3),.A2(A2),.A1(A1),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR4_X1( A1, A2, A3, A4, Z );
input A1, A2, A3, A4;
output Z;
`ifdef FUNCTIONAL // functional //
OR4_X1_func OR4_X1_behav_inst(.A1(A1),.A2(A2),.A3(A3),.A4(A4),.Z(Z));
`else
OR4_X1_func OR4_X1_inst(.A1(A1),.A2(A2),.A3(A3),.A4(A4),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// comb arc A4 --> Z
(A4 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR4_X2( A1, A2, A3, A4, Z );
input A1, A2, A3, A4;
output Z;
`ifdef FUNCTIONAL // functional //
OR4_X2_func OR4_X2_behav_inst(.A1(A1),.A2(A2),.A3(A3),.A4(A4),.Z(Z));
`else
OR4_X2_func OR4_X2_inst(.A1(A1),.A2(A2),.A3(A3),.A4(A4),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// comb arc A4 --> Z
(A4 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module OR4_X4( A4, A3, A2, A1, Z );
input A1, A2, A3, A4;
output Z;
`ifdef FUNCTIONAL // functional //
OR4_X4_func OR4_X4_behav_inst(.A4(A4),.A3(A3),.A2(A2),.A1(A1),.Z(Z));
`else
OR4_X4_func OR4_X4_inst(.A4(A4),.A3(A3),.A2(A2),.A1(A1),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// comb arc A4 --> Z
(A4 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFQ_X1( SE, SI, D, CLK, Q );
input CLK, D, SE, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFQ_X1_func SDFFQ_X1_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.Q(Q),.notifier(notifier));
`else
SDFFQ_X1_func SDFFQ_X1_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
not MGM_G1(MGM_W1,SE);
and MGM_G2(MGM_W2,MGM_W1,MGM_W0);
not MGM_G3(MGM_W3,SI);
and MGM_G4(ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W3,MGM_W2);
not MGM_G5(MGM_W4,D);
not MGM_G6(MGM_W5,SE);
and MGM_G7(MGM_W6,MGM_W5,MGM_W4);
and MGM_G8(ENABLE_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W6);
not MGM_G9(MGM_W7,D);
and MGM_G10(MGM_W8,SE,MGM_W7);
not MGM_G11(MGM_W9,SI);
and MGM_G12(ENABLE_NOT_D_AND_SE_AND_NOT_SI,MGM_W9,MGM_W8);
not MGM_G13(MGM_W10,D);
and MGM_G14(MGM_W11,SE,MGM_W10);
and MGM_G15(ENABLE_NOT_D_AND_SE_AND_SI,SI,MGM_W11);
not MGM_G16(MGM_W12,SE);
and MGM_G17(MGM_W13,MGM_W12,D);
not MGM_G18(MGM_W14,SI);
and MGM_G19(ENABLE_D_AND_NOT_SE_AND_NOT_SI,MGM_W14,MGM_W13);
not MGM_G20(MGM_W15,SE);
and MGM_G21(MGM_W16,MGM_W15,D);
and MGM_G22(ENABLE_D_AND_NOT_SE_AND_SI,SI,MGM_W16);
and MGM_G23(MGM_W17,SE,D);
not MGM_G24(MGM_W18,SI);
and MGM_G25(ENABLE_D_AND_SE_AND_NOT_SI,MGM_W18,MGM_W17);
and MGM_G26(MGM_W19,SE,D);
and MGM_G27(ENABLE_D_AND_SE_AND_SI,SI,MGM_W19);
not MGM_G28(MGM_W20,SE);
not MGM_G29(MGM_W21,SI);
and MGM_G30(ENABLE_NOT_SE_AND_NOT_SI,MGM_W21,MGM_W20);
not MGM_G31(MGM_W22,SE);
and MGM_G32(ENABLE_NOT_SE_AND_SI,SI,MGM_W22);
not MGM_G33(MGM_W23,D);
and MGM_G34(ENABLE_NOT_D_AND_SI,SI,MGM_W23);
not MGM_G35(MGM_W24,SI);
and MGM_G36(ENABLE_D_AND_NOT_SI,MGM_W24,D);
not MGM_G37(MGM_W25,D);
and MGM_G38(ENABLE_NOT_D_AND_SE,SE,MGM_W25);
and MGM_G39(ENABLE_D_AND_SE,SE,D);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),
negedge SI &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),
posedge SI &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFQ_X2( SE, SI, D, CLK, Q );
input CLK, D, SE, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFQ_X2_func SDFFQ_X2_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.Q(Q),.notifier(notifier));
`else
SDFFQ_X2_func SDFFQ_X2_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
not MGM_G1(MGM_W1,SE);
and MGM_G2(MGM_W2,MGM_W1,MGM_W0);
not MGM_G3(MGM_W3,SI);
and MGM_G4(ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W3,MGM_W2);
not MGM_G5(MGM_W4,D);
not MGM_G6(MGM_W5,SE);
and MGM_G7(MGM_W6,MGM_W5,MGM_W4);
and MGM_G8(ENABLE_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W6);
not MGM_G9(MGM_W7,D);
and MGM_G10(MGM_W8,SE,MGM_W7);
not MGM_G11(MGM_W9,SI);
and MGM_G12(ENABLE_NOT_D_AND_SE_AND_NOT_SI,MGM_W9,MGM_W8);
not MGM_G13(MGM_W10,D);
and MGM_G14(MGM_W11,SE,MGM_W10);
and MGM_G15(ENABLE_NOT_D_AND_SE_AND_SI,SI,MGM_W11);
not MGM_G16(MGM_W12,SE);
and MGM_G17(MGM_W13,MGM_W12,D);
not MGM_G18(MGM_W14,SI);
and MGM_G19(ENABLE_D_AND_NOT_SE_AND_NOT_SI,MGM_W14,MGM_W13);
not MGM_G20(MGM_W15,SE);
and MGM_G21(MGM_W16,MGM_W15,D);
and MGM_G22(ENABLE_D_AND_NOT_SE_AND_SI,SI,MGM_W16);
and MGM_G23(MGM_W17,SE,D);
not MGM_G24(MGM_W18,SI);
and MGM_G25(ENABLE_D_AND_SE_AND_NOT_SI,MGM_W18,MGM_W17);
and MGM_G26(MGM_W19,SE,D);
and MGM_G27(ENABLE_D_AND_SE_AND_SI,SI,MGM_W19);
not MGM_G28(MGM_W20,SE);
not MGM_G29(MGM_W21,SI);
and MGM_G30(ENABLE_NOT_SE_AND_NOT_SI,MGM_W21,MGM_W20);
not MGM_G31(MGM_W22,SE);
and MGM_G32(ENABLE_NOT_SE_AND_SI,SI,MGM_W22);
not MGM_G33(MGM_W23,D);
and MGM_G34(ENABLE_NOT_D_AND_SI,SI,MGM_W23);
not MGM_G35(MGM_W24,SI);
and MGM_G36(ENABLE_D_AND_NOT_SI,MGM_W24,D);
not MGM_G37(MGM_W25,D);
and MGM_G38(ENABLE_NOT_D_AND_SE,SE,MGM_W25);
and MGM_G39(ENABLE_D_AND_SE,SE,D);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),
negedge SI &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),
posedge SI &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFQ_X4( SE, SI, D, CLK, Q );
input CLK, D, SE, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFQ_X4_func SDFFQ_X4_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.Q(Q),.notifier(notifier));
`else
SDFFQ_X4_func SDFFQ_X4_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
not MGM_G1(MGM_W1,SE);
and MGM_G2(MGM_W2,MGM_W1,MGM_W0);
not MGM_G3(MGM_W3,SI);
and MGM_G4(ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W3,MGM_W2);
not MGM_G5(MGM_W4,D);
not MGM_G6(MGM_W5,SE);
and MGM_G7(MGM_W6,MGM_W5,MGM_W4);
and MGM_G8(ENABLE_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W6);
not MGM_G9(MGM_W7,D);
and MGM_G10(MGM_W8,SE,MGM_W7);
not MGM_G11(MGM_W9,SI);
and MGM_G12(ENABLE_NOT_D_AND_SE_AND_NOT_SI,MGM_W9,MGM_W8);
not MGM_G13(MGM_W10,D);
and MGM_G14(MGM_W11,SE,MGM_W10);
and MGM_G15(ENABLE_NOT_D_AND_SE_AND_SI,SI,MGM_W11);
not MGM_G16(MGM_W12,SE);
and MGM_G17(MGM_W13,MGM_W12,D);
not MGM_G18(MGM_W14,SI);
and MGM_G19(ENABLE_D_AND_NOT_SE_AND_NOT_SI,MGM_W14,MGM_W13);
not MGM_G20(MGM_W15,SE);
and MGM_G21(MGM_W16,MGM_W15,D);
and MGM_G22(ENABLE_D_AND_NOT_SE_AND_SI,SI,MGM_W16);
and MGM_G23(MGM_W17,SE,D);
not MGM_G24(MGM_W18,SI);
and MGM_G25(ENABLE_D_AND_SE_AND_NOT_SI,MGM_W18,MGM_W17);
and MGM_G26(MGM_W19,SE,D);
and MGM_G27(ENABLE_D_AND_SE_AND_SI,SI,MGM_W19);
not MGM_G28(MGM_W20,SE);
not MGM_G29(MGM_W21,SI);
and MGM_G30(ENABLE_NOT_SE_AND_NOT_SI,MGM_W21,MGM_W20);
not MGM_G31(MGM_W22,SE);
and MGM_G32(ENABLE_NOT_SE_AND_SI,SI,MGM_W22);
not MGM_G33(MGM_W23,D);
and MGM_G34(ENABLE_NOT_D_AND_SI,SI,MGM_W23);
not MGM_G35(MGM_W24,SI);
and MGM_G36(ENABLE_D_AND_NOT_SI,MGM_W24,D);
not MGM_G37(MGM_W25,D);
and MGM_G38(ENABLE_NOT_D_AND_SE,SE,MGM_W25);
and MGM_G39(ENABLE_D_AND_SE,SE,D);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),
negedge SI &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),
posedge SI &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFRNQ_X1( SE, SI, D, CLK, RN, Q );
input CLK, D, RN, SE, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFRNQ_X1_func SDFFRNQ_X1_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.RN(RN),.Q(Q),.notifier(notifier));
`else
SDFFRNQ_X1_func SDFFRNQ_X1_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
not MGM_G2(MGM_W2,SE);
and MGM_G3(MGM_W3,MGM_W2,MGM_W1);
not MGM_G4(MGM_W4,SI);
and MGM_G5(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W4,MGM_W3);
not MGM_G6(MGM_W5,D);
and MGM_G7(MGM_W6,RN,MGM_W5);
not MGM_G8(MGM_W7,SE);
and MGM_G9(MGM_W8,MGM_W7,MGM_W6);
and MGM_G10(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W8);
not MGM_G11(MGM_W9,D);
and MGM_G12(MGM_W10,RN,MGM_W9);
and MGM_G13(MGM_W11,SE,MGM_W10);
not MGM_G14(MGM_W12,SI);
and MGM_G15(ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W12,MGM_W11);
not MGM_G16(MGM_W13,D);
and MGM_G17(MGM_W14,RN,MGM_W13);
and MGM_G18(MGM_W15,SE,MGM_W14);
and MGM_G19(ENABLE_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W15);
and MGM_G20(MGM_W16,RN,D);
not MGM_G21(MGM_W17,SE);
and MGM_G22(MGM_W18,MGM_W17,MGM_W16);
not MGM_G23(MGM_W19,SI);
and MGM_G24(ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W19,MGM_W18);
and MGM_G25(MGM_W20,RN,D);
not MGM_G26(MGM_W21,SE);
and MGM_G27(MGM_W22,MGM_W21,MGM_W20);
and MGM_G28(ENABLE_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W22);
and MGM_G29(MGM_W23,RN,D);
and MGM_G30(MGM_W24,SE,MGM_W23);
not MGM_G31(MGM_W25,SI);
and MGM_G32(ENABLE_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W25,MGM_W24);
and MGM_G33(MGM_W26,RN,D);
and MGM_G34(MGM_W27,SE,MGM_W26);
and MGM_G35(ENABLE_D_AND_RN_AND_SE_AND_SI,SI,MGM_W27);
not MGM_G36(MGM_W28,SE);
and MGM_G37(MGM_W29,MGM_W28,RN);
not MGM_G38(MGM_W30,SI);
and MGM_G39(ENABLE_RN_AND_NOT_SE_AND_NOT_SI,MGM_W30,MGM_W29);
not MGM_G40(MGM_W31,SE);
and MGM_G41(MGM_W32,MGM_W31,RN);
and MGM_G42(ENABLE_RN_AND_NOT_SE_AND_SI,SI,MGM_W32);
not MGM_G43(MGM_W33,D);
and MGM_G44(MGM_W34,SE,MGM_W33);
and MGM_G45(ENABLE_NOT_D_AND_SE_AND_SI,SI,MGM_W34);
not MGM_G46(MGM_W35,SE);
and MGM_G47(MGM_W36,MGM_W35,D);
not MGM_G48(MGM_W37,SI);
and MGM_G49(ENABLE_D_AND_NOT_SE_AND_NOT_SI,MGM_W37,MGM_W36);
not MGM_G50(MGM_W38,SE);
and MGM_G51(MGM_W39,MGM_W38,D);
and MGM_G52(ENABLE_D_AND_NOT_SE_AND_SI,SI,MGM_W39);
and MGM_G53(MGM_W40,SE,D);
and MGM_G54(ENABLE_D_AND_SE_AND_SI,SI,MGM_W40);
not MGM_G55(MGM_W41,CLK);
not MGM_G56(MGM_W42,D);
and MGM_G57(MGM_W43,MGM_W42,MGM_W41);
not MGM_G58(MGM_W44,SE);
and MGM_G59(MGM_W45,MGM_W44,MGM_W43);
not MGM_G60(MGM_W46,SI);
and MGM_G61(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W46,MGM_W45);
not MGM_G62(MGM_W47,CLK);
not MGM_G63(MGM_W48,D);
and MGM_G64(MGM_W49,MGM_W48,MGM_W47);
not MGM_G65(MGM_W50,SE);
and MGM_G66(MGM_W51,MGM_W50,MGM_W49);
and MGM_G67(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W51);
not MGM_G68(MGM_W52,CLK);
not MGM_G69(MGM_W53,D);
and MGM_G70(MGM_W54,MGM_W53,MGM_W52);
and MGM_G71(MGM_W55,SE,MGM_W54);
not MGM_G72(MGM_W56,SI);
and MGM_G73(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W56,MGM_W55);
not MGM_G74(MGM_W57,CLK);
not MGM_G75(MGM_W58,D);
and MGM_G76(MGM_W59,MGM_W58,MGM_W57);
and MGM_G77(MGM_W60,SE,MGM_W59);
and MGM_G78(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W60);
not MGM_G79(MGM_W61,CLK);
and MGM_G80(MGM_W62,D,MGM_W61);
not MGM_G81(MGM_W63,SE);
and MGM_G82(MGM_W64,MGM_W63,MGM_W62);
not MGM_G83(MGM_W65,SI);
and MGM_G84(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W65,MGM_W64);
not MGM_G85(MGM_W66,CLK);
and MGM_G86(MGM_W67,D,MGM_W66);
not MGM_G87(MGM_W68,SE);
and MGM_G88(MGM_W69,MGM_W68,MGM_W67);
and MGM_G89(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W69);
not MGM_G90(MGM_W70,CLK);
and MGM_G91(MGM_W71,D,MGM_W70);
and MGM_G92(MGM_W72,SE,MGM_W71);
not MGM_G93(MGM_W73,SI);
and MGM_G94(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G95(MGM_W74,CLK);
and MGM_G96(MGM_W75,D,MGM_W74);
and MGM_G97(MGM_W76,SE,MGM_W75);
and MGM_G98(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W76);
not MGM_G99(MGM_W77,D);
and MGM_G100(MGM_W78,MGM_W77,CLK);
not MGM_G101(MGM_W79,SE);
and MGM_G102(MGM_W80,MGM_W79,MGM_W78);
not MGM_G103(MGM_W81,SI);
and MGM_G104(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W81,MGM_W80);
not MGM_G105(MGM_W82,D);
and MGM_G106(MGM_W83,MGM_W82,CLK);
not MGM_G107(MGM_W84,SE);
and MGM_G108(MGM_W85,MGM_W84,MGM_W83);
and MGM_G109(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W85);
not MGM_G110(MGM_W86,D);
and MGM_G111(MGM_W87,MGM_W86,CLK);
and MGM_G112(MGM_W88,SE,MGM_W87);
not MGM_G113(MGM_W89,SI);
and MGM_G114(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W89,MGM_W88);
not MGM_G115(MGM_W90,D);
and MGM_G116(MGM_W91,MGM_W90,CLK);
and MGM_G117(MGM_W92,SE,MGM_W91);
and MGM_G118(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W92);
and MGM_G119(MGM_W93,D,CLK);
not MGM_G120(MGM_W94,SE);
and MGM_G121(MGM_W95,MGM_W94,MGM_W93);
not MGM_G122(MGM_W96,SI);
and MGM_G123(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W96,MGM_W95);
and MGM_G124(MGM_W97,D,CLK);
not MGM_G125(MGM_W98,SE);
and MGM_G126(MGM_W99,MGM_W98,MGM_W97);
and MGM_G127(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W99);
and MGM_G128(MGM_W100,D,CLK);
and MGM_G129(MGM_W101,SE,MGM_W100);
not MGM_G130(MGM_W102,SI);
and MGM_G131(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W102,MGM_W101);
and MGM_G132(MGM_W103,D,CLK);
and MGM_G133(MGM_W104,SE,MGM_W103);
and MGM_G134(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W104);
not MGM_G135(MGM_W105,D);
and MGM_G136(MGM_W106,RN,MGM_W105);
and MGM_G137(ENABLE_NOT_D_AND_RN_AND_SI,SI,MGM_W106);
and MGM_G138(MGM_W107,RN,D);
not MGM_G139(MGM_W108,SI);
and MGM_G140(ENABLE_D_AND_RN_AND_NOT_SI,MGM_W108,MGM_W107);
not MGM_G141(MGM_W109,D);
and MGM_G142(MGM_W110,RN,MGM_W109);
and MGM_G143(ENABLE_NOT_D_AND_RN_AND_SE,SE,MGM_W110);
and MGM_G144(MGM_W111,RN,D);
and MGM_G145(ENABLE_D_AND_RN_AND_SE,SE,MGM_W111);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
negedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFRNQ_X2( SE, SI, D, CLK, RN, Q );
input CLK, D, RN, SE, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFRNQ_X2_func SDFFRNQ_X2_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.RN(RN),.Q(Q),.notifier(notifier));
`else
SDFFRNQ_X2_func SDFFRNQ_X2_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
not MGM_G2(MGM_W2,SE);
and MGM_G3(MGM_W3,MGM_W2,MGM_W1);
not MGM_G4(MGM_W4,SI);
and MGM_G5(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W4,MGM_W3);
not MGM_G6(MGM_W5,D);
and MGM_G7(MGM_W6,RN,MGM_W5);
not MGM_G8(MGM_W7,SE);
and MGM_G9(MGM_W8,MGM_W7,MGM_W6);
and MGM_G10(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W8);
not MGM_G11(MGM_W9,D);
and MGM_G12(MGM_W10,RN,MGM_W9);
and MGM_G13(MGM_W11,SE,MGM_W10);
not MGM_G14(MGM_W12,SI);
and MGM_G15(ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W12,MGM_W11);
not MGM_G16(MGM_W13,D);
and MGM_G17(MGM_W14,RN,MGM_W13);
and MGM_G18(MGM_W15,SE,MGM_W14);
and MGM_G19(ENABLE_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W15);
and MGM_G20(MGM_W16,RN,D);
not MGM_G21(MGM_W17,SE);
and MGM_G22(MGM_W18,MGM_W17,MGM_W16);
not MGM_G23(MGM_W19,SI);
and MGM_G24(ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W19,MGM_W18);
and MGM_G25(MGM_W20,RN,D);
not MGM_G26(MGM_W21,SE);
and MGM_G27(MGM_W22,MGM_W21,MGM_W20);
and MGM_G28(ENABLE_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W22);
and MGM_G29(MGM_W23,RN,D);
and MGM_G30(MGM_W24,SE,MGM_W23);
not MGM_G31(MGM_W25,SI);
and MGM_G32(ENABLE_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W25,MGM_W24);
and MGM_G33(MGM_W26,RN,D);
and MGM_G34(MGM_W27,SE,MGM_W26);
and MGM_G35(ENABLE_D_AND_RN_AND_SE_AND_SI,SI,MGM_W27);
not MGM_G36(MGM_W28,SE);
and MGM_G37(MGM_W29,MGM_W28,RN);
not MGM_G38(MGM_W30,SI);
and MGM_G39(ENABLE_RN_AND_NOT_SE_AND_NOT_SI,MGM_W30,MGM_W29);
not MGM_G40(MGM_W31,SE);
and MGM_G41(MGM_W32,MGM_W31,RN);
and MGM_G42(ENABLE_RN_AND_NOT_SE_AND_SI,SI,MGM_W32);
not MGM_G43(MGM_W33,D);
and MGM_G44(MGM_W34,SE,MGM_W33);
and MGM_G45(ENABLE_NOT_D_AND_SE_AND_SI,SI,MGM_W34);
not MGM_G46(MGM_W35,SE);
and MGM_G47(MGM_W36,MGM_W35,D);
not MGM_G48(MGM_W37,SI);
and MGM_G49(ENABLE_D_AND_NOT_SE_AND_NOT_SI,MGM_W37,MGM_W36);
not MGM_G50(MGM_W38,SE);
and MGM_G51(MGM_W39,MGM_W38,D);
and MGM_G52(ENABLE_D_AND_NOT_SE_AND_SI,SI,MGM_W39);
and MGM_G53(MGM_W40,SE,D);
and MGM_G54(ENABLE_D_AND_SE_AND_SI,SI,MGM_W40);
not MGM_G55(MGM_W41,CLK);
not MGM_G56(MGM_W42,D);
and MGM_G57(MGM_W43,MGM_W42,MGM_W41);
not MGM_G58(MGM_W44,SE);
and MGM_G59(MGM_W45,MGM_W44,MGM_W43);
not MGM_G60(MGM_W46,SI);
and MGM_G61(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W46,MGM_W45);
not MGM_G62(MGM_W47,CLK);
not MGM_G63(MGM_W48,D);
and MGM_G64(MGM_W49,MGM_W48,MGM_W47);
not MGM_G65(MGM_W50,SE);
and MGM_G66(MGM_W51,MGM_W50,MGM_W49);
and MGM_G67(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W51);
not MGM_G68(MGM_W52,CLK);
not MGM_G69(MGM_W53,D);
and MGM_G70(MGM_W54,MGM_W53,MGM_W52);
and MGM_G71(MGM_W55,SE,MGM_W54);
not MGM_G72(MGM_W56,SI);
and MGM_G73(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W56,MGM_W55);
not MGM_G74(MGM_W57,CLK);
not MGM_G75(MGM_W58,D);
and MGM_G76(MGM_W59,MGM_W58,MGM_W57);
and MGM_G77(MGM_W60,SE,MGM_W59);
and MGM_G78(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W60);
not MGM_G79(MGM_W61,CLK);
and MGM_G80(MGM_W62,D,MGM_W61);
not MGM_G81(MGM_W63,SE);
and MGM_G82(MGM_W64,MGM_W63,MGM_W62);
not MGM_G83(MGM_W65,SI);
and MGM_G84(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W65,MGM_W64);
not MGM_G85(MGM_W66,CLK);
and MGM_G86(MGM_W67,D,MGM_W66);
not MGM_G87(MGM_W68,SE);
and MGM_G88(MGM_W69,MGM_W68,MGM_W67);
and MGM_G89(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W69);
not MGM_G90(MGM_W70,CLK);
and MGM_G91(MGM_W71,D,MGM_W70);
and MGM_G92(MGM_W72,SE,MGM_W71);
not MGM_G93(MGM_W73,SI);
and MGM_G94(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G95(MGM_W74,CLK);
and MGM_G96(MGM_W75,D,MGM_W74);
and MGM_G97(MGM_W76,SE,MGM_W75);
and MGM_G98(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W76);
not MGM_G99(MGM_W77,D);
and MGM_G100(MGM_W78,MGM_W77,CLK);
not MGM_G101(MGM_W79,SE);
and MGM_G102(MGM_W80,MGM_W79,MGM_W78);
not MGM_G103(MGM_W81,SI);
and MGM_G104(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W81,MGM_W80);
not MGM_G105(MGM_W82,D);
and MGM_G106(MGM_W83,MGM_W82,CLK);
not MGM_G107(MGM_W84,SE);
and MGM_G108(MGM_W85,MGM_W84,MGM_W83);
and MGM_G109(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W85);
not MGM_G110(MGM_W86,D);
and MGM_G111(MGM_W87,MGM_W86,CLK);
and MGM_G112(MGM_W88,SE,MGM_W87);
not MGM_G113(MGM_W89,SI);
and MGM_G114(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W89,MGM_W88);
not MGM_G115(MGM_W90,D);
and MGM_G116(MGM_W91,MGM_W90,CLK);
and MGM_G117(MGM_W92,SE,MGM_W91);
and MGM_G118(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W92);
and MGM_G119(MGM_W93,D,CLK);
not MGM_G120(MGM_W94,SE);
and MGM_G121(MGM_W95,MGM_W94,MGM_W93);
not MGM_G122(MGM_W96,SI);
and MGM_G123(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W96,MGM_W95);
and MGM_G124(MGM_W97,D,CLK);
not MGM_G125(MGM_W98,SE);
and MGM_G126(MGM_W99,MGM_W98,MGM_W97);
and MGM_G127(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W99);
and MGM_G128(MGM_W100,D,CLK);
and MGM_G129(MGM_W101,SE,MGM_W100);
not MGM_G130(MGM_W102,SI);
and MGM_G131(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W102,MGM_W101);
and MGM_G132(MGM_W103,D,CLK);
and MGM_G133(MGM_W104,SE,MGM_W103);
and MGM_G134(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W104);
not MGM_G135(MGM_W105,D);
and MGM_G136(MGM_W106,RN,MGM_W105);
and MGM_G137(ENABLE_NOT_D_AND_RN_AND_SI,SI,MGM_W106);
and MGM_G138(MGM_W107,RN,D);
not MGM_G139(MGM_W108,SI);
and MGM_G140(ENABLE_D_AND_RN_AND_NOT_SI,MGM_W108,MGM_W107);
not MGM_G141(MGM_W109,D);
and MGM_G142(MGM_W110,RN,MGM_W109);
and MGM_G143(ENABLE_NOT_D_AND_RN_AND_SE,SE,MGM_W110);
and MGM_G144(MGM_W111,RN,D);
and MGM_G145(ENABLE_D_AND_RN_AND_SE,SE,MGM_W111);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
negedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFRNQ_X4( SE, SI, D, CLK, RN, Q );
input CLK, D, RN, SE, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFRNQ_X4_func SDFFRNQ_X4_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.RN(RN),.Q(Q),.notifier(notifier));
`else
SDFFRNQ_X4_func SDFFRNQ_X4_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
not MGM_G2(MGM_W2,SE);
and MGM_G3(MGM_W3,MGM_W2,MGM_W1);
not MGM_G4(MGM_W4,SI);
and MGM_G5(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W4,MGM_W3);
not MGM_G6(MGM_W5,D);
and MGM_G7(MGM_W6,RN,MGM_W5);
not MGM_G8(MGM_W7,SE);
and MGM_G9(MGM_W8,MGM_W7,MGM_W6);
and MGM_G10(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W8);
not MGM_G11(MGM_W9,D);
and MGM_G12(MGM_W10,RN,MGM_W9);
and MGM_G13(MGM_W11,SE,MGM_W10);
not MGM_G14(MGM_W12,SI);
and MGM_G15(ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W12,MGM_W11);
not MGM_G16(MGM_W13,D);
and MGM_G17(MGM_W14,RN,MGM_W13);
and MGM_G18(MGM_W15,SE,MGM_W14);
and MGM_G19(ENABLE_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W15);
and MGM_G20(MGM_W16,RN,D);
not MGM_G21(MGM_W17,SE);
and MGM_G22(MGM_W18,MGM_W17,MGM_W16);
not MGM_G23(MGM_W19,SI);
and MGM_G24(ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W19,MGM_W18);
and MGM_G25(MGM_W20,RN,D);
not MGM_G26(MGM_W21,SE);
and MGM_G27(MGM_W22,MGM_W21,MGM_W20);
and MGM_G28(ENABLE_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W22);
and MGM_G29(MGM_W23,RN,D);
and MGM_G30(MGM_W24,SE,MGM_W23);
not MGM_G31(MGM_W25,SI);
and MGM_G32(ENABLE_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W25,MGM_W24);
and MGM_G33(MGM_W26,RN,D);
and MGM_G34(MGM_W27,SE,MGM_W26);
and MGM_G35(ENABLE_D_AND_RN_AND_SE_AND_SI,SI,MGM_W27);
not MGM_G36(MGM_W28,SE);
and MGM_G37(MGM_W29,MGM_W28,RN);
not MGM_G38(MGM_W30,SI);
and MGM_G39(ENABLE_RN_AND_NOT_SE_AND_NOT_SI,MGM_W30,MGM_W29);
not MGM_G40(MGM_W31,SE);
and MGM_G41(MGM_W32,MGM_W31,RN);
and MGM_G42(ENABLE_RN_AND_NOT_SE_AND_SI,SI,MGM_W32);
not MGM_G43(MGM_W33,D);
and MGM_G44(MGM_W34,SE,MGM_W33);
and MGM_G45(ENABLE_NOT_D_AND_SE_AND_SI,SI,MGM_W34);
not MGM_G46(MGM_W35,SE);
and MGM_G47(MGM_W36,MGM_W35,D);
not MGM_G48(MGM_W37,SI);
and MGM_G49(ENABLE_D_AND_NOT_SE_AND_NOT_SI,MGM_W37,MGM_W36);
not MGM_G50(MGM_W38,SE);
and MGM_G51(MGM_W39,MGM_W38,D);
and MGM_G52(ENABLE_D_AND_NOT_SE_AND_SI,SI,MGM_W39);
and MGM_G53(MGM_W40,SE,D);
and MGM_G54(ENABLE_D_AND_SE_AND_SI,SI,MGM_W40);
not MGM_G55(MGM_W41,CLK);
not MGM_G56(MGM_W42,D);
and MGM_G57(MGM_W43,MGM_W42,MGM_W41);
not MGM_G58(MGM_W44,SE);
and MGM_G59(MGM_W45,MGM_W44,MGM_W43);
not MGM_G60(MGM_W46,SI);
and MGM_G61(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W46,MGM_W45);
not MGM_G62(MGM_W47,CLK);
not MGM_G63(MGM_W48,D);
and MGM_G64(MGM_W49,MGM_W48,MGM_W47);
not MGM_G65(MGM_W50,SE);
and MGM_G66(MGM_W51,MGM_W50,MGM_W49);
and MGM_G67(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W51);
not MGM_G68(MGM_W52,CLK);
not MGM_G69(MGM_W53,D);
and MGM_G70(MGM_W54,MGM_W53,MGM_W52);
and MGM_G71(MGM_W55,SE,MGM_W54);
not MGM_G72(MGM_W56,SI);
and MGM_G73(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W56,MGM_W55);
not MGM_G74(MGM_W57,CLK);
not MGM_G75(MGM_W58,D);
and MGM_G76(MGM_W59,MGM_W58,MGM_W57);
and MGM_G77(MGM_W60,SE,MGM_W59);
and MGM_G78(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W60);
not MGM_G79(MGM_W61,CLK);
and MGM_G80(MGM_W62,D,MGM_W61);
not MGM_G81(MGM_W63,SE);
and MGM_G82(MGM_W64,MGM_W63,MGM_W62);
not MGM_G83(MGM_W65,SI);
and MGM_G84(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W65,MGM_W64);
not MGM_G85(MGM_W66,CLK);
and MGM_G86(MGM_W67,D,MGM_W66);
not MGM_G87(MGM_W68,SE);
and MGM_G88(MGM_W69,MGM_W68,MGM_W67);
and MGM_G89(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W69);
not MGM_G90(MGM_W70,CLK);
and MGM_G91(MGM_W71,D,MGM_W70);
and MGM_G92(MGM_W72,SE,MGM_W71);
not MGM_G93(MGM_W73,SI);
and MGM_G94(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G95(MGM_W74,CLK);
and MGM_G96(MGM_W75,D,MGM_W74);
and MGM_G97(MGM_W76,SE,MGM_W75);
and MGM_G98(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W76);
not MGM_G99(MGM_W77,D);
and MGM_G100(MGM_W78,MGM_W77,CLK);
not MGM_G101(MGM_W79,SE);
and MGM_G102(MGM_W80,MGM_W79,MGM_W78);
not MGM_G103(MGM_W81,SI);
and MGM_G104(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W81,MGM_W80);
not MGM_G105(MGM_W82,D);
and MGM_G106(MGM_W83,MGM_W82,CLK);
not MGM_G107(MGM_W84,SE);
and MGM_G108(MGM_W85,MGM_W84,MGM_W83);
and MGM_G109(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W85);
not MGM_G110(MGM_W86,D);
and MGM_G111(MGM_W87,MGM_W86,CLK);
and MGM_G112(MGM_W88,SE,MGM_W87);
not MGM_G113(MGM_W89,SI);
and MGM_G114(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W89,MGM_W88);
not MGM_G115(MGM_W90,D);
and MGM_G116(MGM_W91,MGM_W90,CLK);
and MGM_G117(MGM_W92,SE,MGM_W91);
and MGM_G118(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W92);
and MGM_G119(MGM_W93,D,CLK);
not MGM_G120(MGM_W94,SE);
and MGM_G121(MGM_W95,MGM_W94,MGM_W93);
not MGM_G122(MGM_W96,SI);
and MGM_G123(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W96,MGM_W95);
and MGM_G124(MGM_W97,D,CLK);
not MGM_G125(MGM_W98,SE);
and MGM_G126(MGM_W99,MGM_W98,MGM_W97);
and MGM_G127(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W99);
and MGM_G128(MGM_W100,D,CLK);
and MGM_G129(MGM_W101,SE,MGM_W100);
not MGM_G130(MGM_W102,SI);
and MGM_G131(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W102,MGM_W101);
and MGM_G132(MGM_W103,D,CLK);
and MGM_G133(MGM_W104,SE,MGM_W103);
and MGM_G134(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W104);
not MGM_G135(MGM_W105,D);
and MGM_G136(MGM_W106,RN,MGM_W105);
and MGM_G137(ENABLE_NOT_D_AND_RN_AND_SI,SI,MGM_W106);
and MGM_G138(MGM_W107,RN,D);
not MGM_G139(MGM_W108,SI);
and MGM_G140(ENABLE_D_AND_RN_AND_NOT_SI,MGM_W108,MGM_W107);
not MGM_G141(MGM_W109,D);
and MGM_G142(MGM_W110,RN,MGM_W109);
and MGM_G143(ENABLE_NOT_D_AND_RN_AND_SE,SE,MGM_W110);
and MGM_G144(MGM_W111,RN,D);
and MGM_G145(ENABLE_D_AND_RN_AND_SE,SE,MGM_W111);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
negedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFRSNQ_X1( SE, SI, D, CLK, SETN, RN, Q );
input CLK, D, RN, SE, SETN, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFRSNQ_X1_func SDFFRSNQ_X1_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
SDFFRSNQ_X1_func SDFFRSNQ_X1_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
not MGM_G2(MGM_W2,SE);
and MGM_G3(MGM_W3,MGM_W2,MGM_W1);
and MGM_G4(MGM_W4,SETN,MGM_W3);
not MGM_G5(MGM_W5,SI);
and MGM_G6(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W5,MGM_W4);
not MGM_G7(MGM_W6,D);
and MGM_G8(MGM_W7,RN,MGM_W6);
not MGM_G9(MGM_W8,SE);
and MGM_G10(MGM_W9,MGM_W8,MGM_W7);
and MGM_G11(MGM_W10,SETN,MGM_W9);
and MGM_G12(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W10);
not MGM_G13(MGM_W11,D);
and MGM_G14(MGM_W12,RN,MGM_W11);
and MGM_G15(MGM_W13,SE,MGM_W12);
and MGM_G16(MGM_W14,SETN,MGM_W13);
not MGM_G17(MGM_W15,SI);
and MGM_G18(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI,MGM_W15,MGM_W14);
not MGM_G19(MGM_W16,D);
and MGM_G20(MGM_W17,RN,MGM_W16);
and MGM_G21(MGM_W18,SE,MGM_W17);
and MGM_G22(MGM_W19,SETN,MGM_W18);
and MGM_G23(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI,SI,MGM_W19);
and MGM_G24(MGM_W20,RN,D);
not MGM_G25(MGM_W21,SE);
and MGM_G26(MGM_W22,MGM_W21,MGM_W20);
and MGM_G27(MGM_W23,SETN,MGM_W22);
not MGM_G28(MGM_W24,SI);
and MGM_G29(ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W24,MGM_W23);
and MGM_G30(MGM_W25,RN,D);
not MGM_G31(MGM_W26,SE);
and MGM_G32(MGM_W27,MGM_W26,MGM_W25);
and MGM_G33(MGM_W28,SETN,MGM_W27);
and MGM_G34(ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W28);
and MGM_G35(MGM_W29,RN,D);
and MGM_G36(MGM_W30,SE,MGM_W29);
and MGM_G37(MGM_W31,SETN,MGM_W30);
not MGM_G38(MGM_W32,SI);
and MGM_G39(ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI,MGM_W32,MGM_W31);
and MGM_G40(MGM_W33,RN,D);
and MGM_G41(MGM_W34,SE,MGM_W33);
and MGM_G42(MGM_W35,SETN,MGM_W34);
and MGM_G43(ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI,SI,MGM_W35);
not MGM_G44(MGM_W36,SE);
and MGM_G45(MGM_W37,MGM_W36,RN);
and MGM_G46(MGM_W38,SETN,MGM_W37);
not MGM_G47(MGM_W39,SI);
and MGM_G48(ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W39,MGM_W38);
not MGM_G49(MGM_W40,SE);
and MGM_G50(MGM_W41,MGM_W40,RN);
and MGM_G51(MGM_W42,SETN,MGM_W41);
and MGM_G52(ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W42);
not MGM_G53(MGM_W43,D);
and MGM_G54(MGM_W44,SE,MGM_W43);
and MGM_G55(MGM_W45,SETN,MGM_W44);
and MGM_G56(ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W45);
not MGM_G57(MGM_W46,SE);
and MGM_G58(MGM_W47,MGM_W46,D);
and MGM_G59(MGM_W48,SETN,MGM_W47);
not MGM_G60(MGM_W49,SI);
and MGM_G61(ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W49,MGM_W48);
not MGM_G62(MGM_W50,SE);
and MGM_G63(MGM_W51,MGM_W50,D);
and MGM_G64(MGM_W52,SETN,MGM_W51);
and MGM_G65(ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W52);
and MGM_G66(MGM_W53,SE,D);
and MGM_G67(MGM_W54,SETN,MGM_W53);
and MGM_G68(ENABLE_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W54);
not MGM_G69(MGM_W55,CLK);
not MGM_G70(MGM_W56,D);
and MGM_G71(MGM_W57,MGM_W56,MGM_W55);
not MGM_G72(MGM_W58,SE);
and MGM_G73(MGM_W59,MGM_W58,MGM_W57);
and MGM_G74(MGM_W60,SETN,MGM_W59);
not MGM_G75(MGM_W61,SI);
and MGM_G76(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W61,MGM_W60);
not MGM_G77(MGM_W62,CLK);
not MGM_G78(MGM_W63,D);
and MGM_G79(MGM_W64,MGM_W63,MGM_W62);
not MGM_G80(MGM_W65,SE);
and MGM_G81(MGM_W66,MGM_W65,MGM_W64);
and MGM_G82(MGM_W67,SETN,MGM_W66);
and MGM_G83(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W67);
not MGM_G84(MGM_W68,CLK);
not MGM_G85(MGM_W69,D);
and MGM_G86(MGM_W70,MGM_W69,MGM_W68);
and MGM_G87(MGM_W71,SE,MGM_W70);
and MGM_G88(MGM_W72,SETN,MGM_W71);
not MGM_G89(MGM_W73,SI);
and MGM_G90(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G91(MGM_W74,CLK);
not MGM_G92(MGM_W75,D);
and MGM_G93(MGM_W76,MGM_W75,MGM_W74);
and MGM_G94(MGM_W77,SE,MGM_W76);
and MGM_G95(MGM_W78,SETN,MGM_W77);
and MGM_G96(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W78);
not MGM_G97(MGM_W79,CLK);
and MGM_G98(MGM_W80,D,MGM_W79);
not MGM_G99(MGM_W81,SE);
and MGM_G100(MGM_W82,MGM_W81,MGM_W80);
and MGM_G101(MGM_W83,SETN,MGM_W82);
not MGM_G102(MGM_W84,SI);
and MGM_G103(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W84,MGM_W83);
not MGM_G104(MGM_W85,CLK);
and MGM_G105(MGM_W86,D,MGM_W85);
not MGM_G106(MGM_W87,SE);
and MGM_G107(MGM_W88,MGM_W87,MGM_W86);
and MGM_G108(MGM_W89,SETN,MGM_W88);
and MGM_G109(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W89);
not MGM_G110(MGM_W90,CLK);
and MGM_G111(MGM_W91,D,MGM_W90);
and MGM_G112(MGM_W92,SE,MGM_W91);
and MGM_G113(MGM_W93,SETN,MGM_W92);
not MGM_G114(MGM_W94,SI);
and MGM_G115(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W94,MGM_W93);
not MGM_G116(MGM_W95,CLK);
and MGM_G117(MGM_W96,D,MGM_W95);
and MGM_G118(MGM_W97,SE,MGM_W96);
and MGM_G119(MGM_W98,SETN,MGM_W97);
and MGM_G120(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W98);
not MGM_G121(MGM_W99,D);
and MGM_G122(MGM_W100,MGM_W99,CLK);
not MGM_G123(MGM_W101,SE);
and MGM_G124(MGM_W102,MGM_W101,MGM_W100);
and MGM_G125(MGM_W103,SETN,MGM_W102);
not MGM_G126(MGM_W104,SI);
and MGM_G127(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W104,MGM_W103);
not MGM_G128(MGM_W105,D);
and MGM_G129(MGM_W106,MGM_W105,CLK);
not MGM_G130(MGM_W107,SE);
and MGM_G131(MGM_W108,MGM_W107,MGM_W106);
and MGM_G132(MGM_W109,SETN,MGM_W108);
and MGM_G133(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W109);
not MGM_G134(MGM_W110,D);
and MGM_G135(MGM_W111,MGM_W110,CLK);
and MGM_G136(MGM_W112,SE,MGM_W111);
and MGM_G137(MGM_W113,SETN,MGM_W112);
not MGM_G138(MGM_W114,SI);
and MGM_G139(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W114,MGM_W113);
not MGM_G140(MGM_W115,D);
and MGM_G141(MGM_W116,MGM_W115,CLK);
and MGM_G142(MGM_W117,SE,MGM_W116);
and MGM_G143(MGM_W118,SETN,MGM_W117);
and MGM_G144(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W118);
and MGM_G145(MGM_W119,D,CLK);
not MGM_G146(MGM_W120,SE);
and MGM_G147(MGM_W121,MGM_W120,MGM_W119);
and MGM_G148(MGM_W122,SETN,MGM_W121);
not MGM_G149(MGM_W123,SI);
and MGM_G150(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W123,MGM_W122);
and MGM_G151(MGM_W124,D,CLK);
not MGM_G152(MGM_W125,SE);
and MGM_G153(MGM_W126,MGM_W125,MGM_W124);
and MGM_G154(MGM_W127,SETN,MGM_W126);
and MGM_G155(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W127);
and MGM_G156(MGM_W128,D,CLK);
and MGM_G157(MGM_W129,SE,MGM_W128);
and MGM_G158(MGM_W130,SETN,MGM_W129);
not MGM_G159(MGM_W131,SI);
and MGM_G160(ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W131,MGM_W130);
and MGM_G161(MGM_W132,D,CLK);
and MGM_G162(MGM_W133,SE,MGM_W132);
and MGM_G163(MGM_W134,SETN,MGM_W133);
and MGM_G164(ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W134);
not MGM_G165(MGM_W135,CLK);
not MGM_G166(MGM_W136,D);
and MGM_G167(MGM_W137,MGM_W136,MGM_W135);
not MGM_G168(MGM_W138,SE);
and MGM_G169(MGM_W139,MGM_W138,MGM_W137);
not MGM_G170(MGM_W140,SI);
and MGM_G171(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W140,MGM_W139);
not MGM_G172(MGM_W141,CLK);
not MGM_G173(MGM_W142,D);
and MGM_G174(MGM_W143,MGM_W142,MGM_W141);
not MGM_G175(MGM_W144,SE);
and MGM_G176(MGM_W145,MGM_W144,MGM_W143);
and MGM_G177(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W145);
not MGM_G178(MGM_W146,CLK);
not MGM_G179(MGM_W147,D);
and MGM_G180(MGM_W148,MGM_W147,MGM_W146);
and MGM_G181(MGM_W149,SE,MGM_W148);
not MGM_G182(MGM_W150,SI);
and MGM_G183(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W150,MGM_W149);
not MGM_G184(MGM_W151,CLK);
not MGM_G185(MGM_W152,D);
and MGM_G186(MGM_W153,MGM_W152,MGM_W151);
and MGM_G187(MGM_W154,SE,MGM_W153);
and MGM_G188(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W154);
not MGM_G189(MGM_W155,CLK);
and MGM_G190(MGM_W156,D,MGM_W155);
not MGM_G191(MGM_W157,SE);
and MGM_G192(MGM_W158,MGM_W157,MGM_W156);
not MGM_G193(MGM_W159,SI);
and MGM_G194(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W159,MGM_W158);
not MGM_G195(MGM_W160,CLK);
and MGM_G196(MGM_W161,D,MGM_W160);
not MGM_G197(MGM_W162,SE);
and MGM_G198(MGM_W163,MGM_W162,MGM_W161);
and MGM_G199(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W163);
not MGM_G200(MGM_W164,CLK);
and MGM_G201(MGM_W165,D,MGM_W164);
and MGM_G202(MGM_W166,SE,MGM_W165);
not MGM_G203(MGM_W167,SI);
and MGM_G204(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W167,MGM_W166);
not MGM_G205(MGM_W168,CLK);
and MGM_G206(MGM_W169,D,MGM_W168);
and MGM_G207(MGM_W170,SE,MGM_W169);
and MGM_G208(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W170);
not MGM_G209(MGM_W171,D);
and MGM_G210(MGM_W172,MGM_W171,CLK);
not MGM_G211(MGM_W173,SE);
and MGM_G212(MGM_W174,MGM_W173,MGM_W172);
not MGM_G213(MGM_W175,SI);
and MGM_G214(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W175,MGM_W174);
not MGM_G215(MGM_W176,D);
and MGM_G216(MGM_W177,MGM_W176,CLK);
not MGM_G217(MGM_W178,SE);
and MGM_G218(MGM_W179,MGM_W178,MGM_W177);
and MGM_G219(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W179);
not MGM_G220(MGM_W180,D);
and MGM_G221(MGM_W181,MGM_W180,CLK);
and MGM_G222(MGM_W182,SE,MGM_W181);
not MGM_G223(MGM_W183,SI);
and MGM_G224(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W183,MGM_W182);
not MGM_G225(MGM_W184,D);
and MGM_G226(MGM_W185,MGM_W184,CLK);
and MGM_G227(MGM_W186,SE,MGM_W185);
and MGM_G228(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W186);
and MGM_G229(MGM_W187,D,CLK);
not MGM_G230(MGM_W188,SE);
and MGM_G231(MGM_W189,MGM_W188,MGM_W187);
not MGM_G232(MGM_W190,SI);
and MGM_G233(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W190,MGM_W189);
and MGM_G234(MGM_W191,D,CLK);
not MGM_G235(MGM_W192,SE);
and MGM_G236(MGM_W193,MGM_W192,MGM_W191);
and MGM_G237(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W193);
and MGM_G238(MGM_W194,D,CLK);
and MGM_G239(MGM_W195,SE,MGM_W194);
not MGM_G240(MGM_W196,SI);
and MGM_G241(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W196,MGM_W195);
and MGM_G242(MGM_W197,D,CLK);
and MGM_G243(MGM_W198,SE,MGM_W197);
and MGM_G244(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W198);
not MGM_G245(MGM_W199,D);
and MGM_G246(MGM_W200,RN,MGM_W199);
and MGM_G247(MGM_W201,SETN,MGM_W200);
and MGM_G248(ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI,SI,MGM_W201);
and MGM_G249(MGM_W202,RN,D);
and MGM_G250(MGM_W203,SETN,MGM_W202);
not MGM_G251(MGM_W204,SI);
and MGM_G252(ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI,MGM_W204,MGM_W203);
not MGM_G253(MGM_W205,D);
and MGM_G254(MGM_W206,RN,MGM_W205);
not MGM_G255(MGM_W207,SE);
and MGM_G256(MGM_W208,MGM_W207,MGM_W206);
not MGM_G257(MGM_W209,SI);
and MGM_G258(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W209,MGM_W208);
not MGM_G259(MGM_W210,D);
and MGM_G260(MGM_W211,RN,MGM_W210);
not MGM_G261(MGM_W212,SE);
and MGM_G262(MGM_W213,MGM_W212,MGM_W211);
and MGM_G263(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W213);
not MGM_G264(MGM_W214,D);
and MGM_G265(MGM_W215,RN,MGM_W214);
and MGM_G266(MGM_W216,SE,MGM_W215);
not MGM_G267(MGM_W217,SI);
and MGM_G268(ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W217,MGM_W216);
and MGM_G269(MGM_W218,RN,D);
and MGM_G270(MGM_W219,SE,MGM_W218);
not MGM_G271(MGM_W220,SI);
and MGM_G272(ENABLE_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W220,MGM_W219);
not MGM_G273(MGM_W221,CLK);
not MGM_G274(MGM_W222,D);
and MGM_G275(MGM_W223,MGM_W222,MGM_W221);
and MGM_G276(MGM_W224,RN,MGM_W223);
not MGM_G277(MGM_W225,SE);
and MGM_G278(MGM_W226,MGM_W225,MGM_W224);
not MGM_G279(MGM_W227,SI);
and MGM_G280(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W227,MGM_W226);
not MGM_G281(MGM_W228,CLK);
not MGM_G282(MGM_W229,D);
and MGM_G283(MGM_W230,MGM_W229,MGM_W228);
and MGM_G284(MGM_W231,RN,MGM_W230);
not MGM_G285(MGM_W232,SE);
and MGM_G286(MGM_W233,MGM_W232,MGM_W231);
and MGM_G287(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W233);
not MGM_G288(MGM_W234,CLK);
not MGM_G289(MGM_W235,D);
and MGM_G290(MGM_W236,MGM_W235,MGM_W234);
and MGM_G291(MGM_W237,RN,MGM_W236);
and MGM_G292(MGM_W238,SE,MGM_W237);
not MGM_G293(MGM_W239,SI);
and MGM_G294(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W239,MGM_W238);
not MGM_G295(MGM_W240,CLK);
not MGM_G296(MGM_W241,D);
and MGM_G297(MGM_W242,MGM_W241,MGM_W240);
and MGM_G298(MGM_W243,RN,MGM_W242);
and MGM_G299(MGM_W244,SE,MGM_W243);
and MGM_G300(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W244);
not MGM_G301(MGM_W245,CLK);
and MGM_G302(MGM_W246,D,MGM_W245);
and MGM_G303(MGM_W247,RN,MGM_W246);
not MGM_G304(MGM_W248,SE);
and MGM_G305(MGM_W249,MGM_W248,MGM_W247);
not MGM_G306(MGM_W250,SI);
and MGM_G307(ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W250,MGM_W249);
not MGM_G308(MGM_W251,CLK);
and MGM_G309(MGM_W252,D,MGM_W251);
and MGM_G310(MGM_W253,RN,MGM_W252);
not MGM_G311(MGM_W254,SE);
and MGM_G312(MGM_W255,MGM_W254,MGM_W253);
and MGM_G313(ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W255);
not MGM_G314(MGM_W256,CLK);
and MGM_G315(MGM_W257,D,MGM_W256);
and MGM_G316(MGM_W258,RN,MGM_W257);
and MGM_G317(MGM_W259,SE,MGM_W258);
not MGM_G318(MGM_W260,SI);
and MGM_G319(ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W260,MGM_W259);
not MGM_G320(MGM_W261,CLK);
and MGM_G321(MGM_W262,D,MGM_W261);
and MGM_G322(MGM_W263,RN,MGM_W262);
and MGM_G323(MGM_W264,SE,MGM_W263);
and MGM_G324(ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_SI,SI,MGM_W264);
not MGM_G325(MGM_W265,D);
and MGM_G326(MGM_W266,MGM_W265,CLK);
and MGM_G327(MGM_W267,RN,MGM_W266);
not MGM_G328(MGM_W268,SE);
and MGM_G329(MGM_W269,MGM_W268,MGM_W267);
not MGM_G330(MGM_W270,SI);
and MGM_G331(ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W270,MGM_W269);
not MGM_G332(MGM_W271,D);
and MGM_G333(MGM_W272,MGM_W271,CLK);
and MGM_G334(MGM_W273,RN,MGM_W272);
not MGM_G335(MGM_W274,SE);
and MGM_G336(MGM_W275,MGM_W274,MGM_W273);
and MGM_G337(ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W275);
not MGM_G338(MGM_W276,D);
and MGM_G339(MGM_W277,MGM_W276,CLK);
and MGM_G340(MGM_W278,RN,MGM_W277);
and MGM_G341(MGM_W279,SE,MGM_W278);
not MGM_G342(MGM_W280,SI);
and MGM_G343(ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W280,MGM_W279);
not MGM_G344(MGM_W281,D);
and MGM_G345(MGM_W282,MGM_W281,CLK);
and MGM_G346(MGM_W283,RN,MGM_W282);
and MGM_G347(MGM_W284,SE,MGM_W283);
and MGM_G348(ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W284);
and MGM_G349(MGM_W285,D,CLK);
and MGM_G350(MGM_W286,RN,MGM_W285);
not MGM_G351(MGM_W287,SE);
and MGM_G352(MGM_W288,MGM_W287,MGM_W286);
not MGM_G353(MGM_W289,SI);
and MGM_G354(ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W289,MGM_W288);
and MGM_G355(MGM_W290,D,CLK);
and MGM_G356(MGM_W291,RN,MGM_W290);
not MGM_G357(MGM_W292,SE);
and MGM_G358(MGM_W293,MGM_W292,MGM_W291);
and MGM_G359(ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W293);
and MGM_G360(MGM_W294,D,CLK);
and MGM_G361(MGM_W295,RN,MGM_W294);
and MGM_G362(MGM_W296,SE,MGM_W295);
not MGM_G363(MGM_W297,SI);
and MGM_G364(ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W297,MGM_W296);
and MGM_G365(MGM_W298,D,CLK);
and MGM_G366(MGM_W299,RN,MGM_W298);
and MGM_G367(MGM_W300,SE,MGM_W299);
and MGM_G368(ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_SI,SI,MGM_W300);
not MGM_G369(MGM_W301,D);
and MGM_G370(MGM_W302,RN,MGM_W301);
and MGM_G371(MGM_W303,SE,MGM_W302);
and MGM_G372(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN,SETN,MGM_W303);
and MGM_G373(MGM_W304,RN,D);
and MGM_G374(MGM_W305,SE,MGM_W304);
and MGM_G375(ENABLE_D_AND_RN_AND_SE_AND_SETN,SETN,MGM_W305);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFRSNQ_X2( SE, SI, D, CLK, SETN, RN, Q );
input CLK, D, RN, SE, SETN, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFRSNQ_X2_func SDFFRSNQ_X2_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
SDFFRSNQ_X2_func SDFFRSNQ_X2_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
not MGM_G2(MGM_W2,SE);
and MGM_G3(MGM_W3,MGM_W2,MGM_W1);
and MGM_G4(MGM_W4,SETN,MGM_W3);
not MGM_G5(MGM_W5,SI);
and MGM_G6(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W5,MGM_W4);
not MGM_G7(MGM_W6,D);
and MGM_G8(MGM_W7,RN,MGM_W6);
not MGM_G9(MGM_W8,SE);
and MGM_G10(MGM_W9,MGM_W8,MGM_W7);
and MGM_G11(MGM_W10,SETN,MGM_W9);
and MGM_G12(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W10);
not MGM_G13(MGM_W11,D);
and MGM_G14(MGM_W12,RN,MGM_W11);
and MGM_G15(MGM_W13,SE,MGM_W12);
and MGM_G16(MGM_W14,SETN,MGM_W13);
not MGM_G17(MGM_W15,SI);
and MGM_G18(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI,MGM_W15,MGM_W14);
not MGM_G19(MGM_W16,D);
and MGM_G20(MGM_W17,RN,MGM_W16);
and MGM_G21(MGM_W18,SE,MGM_W17);
and MGM_G22(MGM_W19,SETN,MGM_W18);
and MGM_G23(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI,SI,MGM_W19);
and MGM_G24(MGM_W20,RN,D);
not MGM_G25(MGM_W21,SE);
and MGM_G26(MGM_W22,MGM_W21,MGM_W20);
and MGM_G27(MGM_W23,SETN,MGM_W22);
not MGM_G28(MGM_W24,SI);
and MGM_G29(ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W24,MGM_W23);
and MGM_G30(MGM_W25,RN,D);
not MGM_G31(MGM_W26,SE);
and MGM_G32(MGM_W27,MGM_W26,MGM_W25);
and MGM_G33(MGM_W28,SETN,MGM_W27);
and MGM_G34(ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W28);
and MGM_G35(MGM_W29,RN,D);
and MGM_G36(MGM_W30,SE,MGM_W29);
and MGM_G37(MGM_W31,SETN,MGM_W30);
not MGM_G38(MGM_W32,SI);
and MGM_G39(ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI,MGM_W32,MGM_W31);
and MGM_G40(MGM_W33,RN,D);
and MGM_G41(MGM_W34,SE,MGM_W33);
and MGM_G42(MGM_W35,SETN,MGM_W34);
and MGM_G43(ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI,SI,MGM_W35);
not MGM_G44(MGM_W36,SE);
and MGM_G45(MGM_W37,MGM_W36,RN);
and MGM_G46(MGM_W38,SETN,MGM_W37);
not MGM_G47(MGM_W39,SI);
and MGM_G48(ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W39,MGM_W38);
not MGM_G49(MGM_W40,SE);
and MGM_G50(MGM_W41,MGM_W40,RN);
and MGM_G51(MGM_W42,SETN,MGM_W41);
and MGM_G52(ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W42);
not MGM_G53(MGM_W43,D);
and MGM_G54(MGM_W44,SE,MGM_W43);
and MGM_G55(MGM_W45,SETN,MGM_W44);
and MGM_G56(ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W45);
not MGM_G57(MGM_W46,SE);
and MGM_G58(MGM_W47,MGM_W46,D);
and MGM_G59(MGM_W48,SETN,MGM_W47);
not MGM_G60(MGM_W49,SI);
and MGM_G61(ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W49,MGM_W48);
not MGM_G62(MGM_W50,SE);
and MGM_G63(MGM_W51,MGM_W50,D);
and MGM_G64(MGM_W52,SETN,MGM_W51);
and MGM_G65(ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W52);
and MGM_G66(MGM_W53,SE,D);
and MGM_G67(MGM_W54,SETN,MGM_W53);
and MGM_G68(ENABLE_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W54);
not MGM_G69(MGM_W55,CLK);
not MGM_G70(MGM_W56,D);
and MGM_G71(MGM_W57,MGM_W56,MGM_W55);
not MGM_G72(MGM_W58,SE);
and MGM_G73(MGM_W59,MGM_W58,MGM_W57);
and MGM_G74(MGM_W60,SETN,MGM_W59);
not MGM_G75(MGM_W61,SI);
and MGM_G76(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W61,MGM_W60);
not MGM_G77(MGM_W62,CLK);
not MGM_G78(MGM_W63,D);
and MGM_G79(MGM_W64,MGM_W63,MGM_W62);
not MGM_G80(MGM_W65,SE);
and MGM_G81(MGM_W66,MGM_W65,MGM_W64);
and MGM_G82(MGM_W67,SETN,MGM_W66);
and MGM_G83(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W67);
not MGM_G84(MGM_W68,CLK);
not MGM_G85(MGM_W69,D);
and MGM_G86(MGM_W70,MGM_W69,MGM_W68);
and MGM_G87(MGM_W71,SE,MGM_W70);
and MGM_G88(MGM_W72,SETN,MGM_W71);
not MGM_G89(MGM_W73,SI);
and MGM_G90(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G91(MGM_W74,CLK);
not MGM_G92(MGM_W75,D);
and MGM_G93(MGM_W76,MGM_W75,MGM_W74);
and MGM_G94(MGM_W77,SE,MGM_W76);
and MGM_G95(MGM_W78,SETN,MGM_W77);
and MGM_G96(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W78);
not MGM_G97(MGM_W79,CLK);
and MGM_G98(MGM_W80,D,MGM_W79);
not MGM_G99(MGM_W81,SE);
and MGM_G100(MGM_W82,MGM_W81,MGM_W80);
and MGM_G101(MGM_W83,SETN,MGM_W82);
not MGM_G102(MGM_W84,SI);
and MGM_G103(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W84,MGM_W83);
not MGM_G104(MGM_W85,CLK);
and MGM_G105(MGM_W86,D,MGM_W85);
not MGM_G106(MGM_W87,SE);
and MGM_G107(MGM_W88,MGM_W87,MGM_W86);
and MGM_G108(MGM_W89,SETN,MGM_W88);
and MGM_G109(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W89);
not MGM_G110(MGM_W90,CLK);
and MGM_G111(MGM_W91,D,MGM_W90);
and MGM_G112(MGM_W92,SE,MGM_W91);
and MGM_G113(MGM_W93,SETN,MGM_W92);
not MGM_G114(MGM_W94,SI);
and MGM_G115(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W94,MGM_W93);
not MGM_G116(MGM_W95,CLK);
and MGM_G117(MGM_W96,D,MGM_W95);
and MGM_G118(MGM_W97,SE,MGM_W96);
and MGM_G119(MGM_W98,SETN,MGM_W97);
and MGM_G120(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W98);
not MGM_G121(MGM_W99,D);
and MGM_G122(MGM_W100,MGM_W99,CLK);
not MGM_G123(MGM_W101,SE);
and MGM_G124(MGM_W102,MGM_W101,MGM_W100);
and MGM_G125(MGM_W103,SETN,MGM_W102);
not MGM_G126(MGM_W104,SI);
and MGM_G127(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W104,MGM_W103);
not MGM_G128(MGM_W105,D);
and MGM_G129(MGM_W106,MGM_W105,CLK);
not MGM_G130(MGM_W107,SE);
and MGM_G131(MGM_W108,MGM_W107,MGM_W106);
and MGM_G132(MGM_W109,SETN,MGM_W108);
and MGM_G133(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W109);
not MGM_G134(MGM_W110,D);
and MGM_G135(MGM_W111,MGM_W110,CLK);
and MGM_G136(MGM_W112,SE,MGM_W111);
and MGM_G137(MGM_W113,SETN,MGM_W112);
not MGM_G138(MGM_W114,SI);
and MGM_G139(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W114,MGM_W113);
not MGM_G140(MGM_W115,D);
and MGM_G141(MGM_W116,MGM_W115,CLK);
and MGM_G142(MGM_W117,SE,MGM_W116);
and MGM_G143(MGM_W118,SETN,MGM_W117);
and MGM_G144(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W118);
and MGM_G145(MGM_W119,D,CLK);
not MGM_G146(MGM_W120,SE);
and MGM_G147(MGM_W121,MGM_W120,MGM_W119);
and MGM_G148(MGM_W122,SETN,MGM_W121);
not MGM_G149(MGM_W123,SI);
and MGM_G150(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W123,MGM_W122);
and MGM_G151(MGM_W124,D,CLK);
not MGM_G152(MGM_W125,SE);
and MGM_G153(MGM_W126,MGM_W125,MGM_W124);
and MGM_G154(MGM_W127,SETN,MGM_W126);
and MGM_G155(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W127);
and MGM_G156(MGM_W128,D,CLK);
and MGM_G157(MGM_W129,SE,MGM_W128);
and MGM_G158(MGM_W130,SETN,MGM_W129);
not MGM_G159(MGM_W131,SI);
and MGM_G160(ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W131,MGM_W130);
and MGM_G161(MGM_W132,D,CLK);
and MGM_G162(MGM_W133,SE,MGM_W132);
and MGM_G163(MGM_W134,SETN,MGM_W133);
and MGM_G164(ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W134);
not MGM_G165(MGM_W135,CLK);
not MGM_G166(MGM_W136,D);
and MGM_G167(MGM_W137,MGM_W136,MGM_W135);
not MGM_G168(MGM_W138,SE);
and MGM_G169(MGM_W139,MGM_W138,MGM_W137);
not MGM_G170(MGM_W140,SI);
and MGM_G171(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W140,MGM_W139);
not MGM_G172(MGM_W141,CLK);
not MGM_G173(MGM_W142,D);
and MGM_G174(MGM_W143,MGM_W142,MGM_W141);
not MGM_G175(MGM_W144,SE);
and MGM_G176(MGM_W145,MGM_W144,MGM_W143);
and MGM_G177(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W145);
not MGM_G178(MGM_W146,CLK);
not MGM_G179(MGM_W147,D);
and MGM_G180(MGM_W148,MGM_W147,MGM_W146);
and MGM_G181(MGM_W149,SE,MGM_W148);
not MGM_G182(MGM_W150,SI);
and MGM_G183(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W150,MGM_W149);
not MGM_G184(MGM_W151,CLK);
not MGM_G185(MGM_W152,D);
and MGM_G186(MGM_W153,MGM_W152,MGM_W151);
and MGM_G187(MGM_W154,SE,MGM_W153);
and MGM_G188(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W154);
not MGM_G189(MGM_W155,CLK);
and MGM_G190(MGM_W156,D,MGM_W155);
not MGM_G191(MGM_W157,SE);
and MGM_G192(MGM_W158,MGM_W157,MGM_W156);
not MGM_G193(MGM_W159,SI);
and MGM_G194(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W159,MGM_W158);
not MGM_G195(MGM_W160,CLK);
and MGM_G196(MGM_W161,D,MGM_W160);
not MGM_G197(MGM_W162,SE);
and MGM_G198(MGM_W163,MGM_W162,MGM_W161);
and MGM_G199(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W163);
not MGM_G200(MGM_W164,CLK);
and MGM_G201(MGM_W165,D,MGM_W164);
and MGM_G202(MGM_W166,SE,MGM_W165);
not MGM_G203(MGM_W167,SI);
and MGM_G204(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W167,MGM_W166);
not MGM_G205(MGM_W168,CLK);
and MGM_G206(MGM_W169,D,MGM_W168);
and MGM_G207(MGM_W170,SE,MGM_W169);
and MGM_G208(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W170);
not MGM_G209(MGM_W171,D);
and MGM_G210(MGM_W172,MGM_W171,CLK);
not MGM_G211(MGM_W173,SE);
and MGM_G212(MGM_W174,MGM_W173,MGM_W172);
not MGM_G213(MGM_W175,SI);
and MGM_G214(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W175,MGM_W174);
not MGM_G215(MGM_W176,D);
and MGM_G216(MGM_W177,MGM_W176,CLK);
not MGM_G217(MGM_W178,SE);
and MGM_G218(MGM_W179,MGM_W178,MGM_W177);
and MGM_G219(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W179);
not MGM_G220(MGM_W180,D);
and MGM_G221(MGM_W181,MGM_W180,CLK);
and MGM_G222(MGM_W182,SE,MGM_W181);
not MGM_G223(MGM_W183,SI);
and MGM_G224(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W183,MGM_W182);
not MGM_G225(MGM_W184,D);
and MGM_G226(MGM_W185,MGM_W184,CLK);
and MGM_G227(MGM_W186,SE,MGM_W185);
and MGM_G228(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W186);
and MGM_G229(MGM_W187,D,CLK);
not MGM_G230(MGM_W188,SE);
and MGM_G231(MGM_W189,MGM_W188,MGM_W187);
not MGM_G232(MGM_W190,SI);
and MGM_G233(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W190,MGM_W189);
and MGM_G234(MGM_W191,D,CLK);
not MGM_G235(MGM_W192,SE);
and MGM_G236(MGM_W193,MGM_W192,MGM_W191);
and MGM_G237(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W193);
and MGM_G238(MGM_W194,D,CLK);
and MGM_G239(MGM_W195,SE,MGM_W194);
not MGM_G240(MGM_W196,SI);
and MGM_G241(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W196,MGM_W195);
and MGM_G242(MGM_W197,D,CLK);
and MGM_G243(MGM_W198,SE,MGM_W197);
and MGM_G244(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W198);
not MGM_G245(MGM_W199,D);
and MGM_G246(MGM_W200,RN,MGM_W199);
and MGM_G247(MGM_W201,SETN,MGM_W200);
and MGM_G248(ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI,SI,MGM_W201);
and MGM_G249(MGM_W202,RN,D);
and MGM_G250(MGM_W203,SETN,MGM_W202);
not MGM_G251(MGM_W204,SI);
and MGM_G252(ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI,MGM_W204,MGM_W203);
not MGM_G253(MGM_W205,D);
and MGM_G254(MGM_W206,RN,MGM_W205);
not MGM_G255(MGM_W207,SE);
and MGM_G256(MGM_W208,MGM_W207,MGM_W206);
not MGM_G257(MGM_W209,SI);
and MGM_G258(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W209,MGM_W208);
not MGM_G259(MGM_W210,D);
and MGM_G260(MGM_W211,RN,MGM_W210);
not MGM_G261(MGM_W212,SE);
and MGM_G262(MGM_W213,MGM_W212,MGM_W211);
and MGM_G263(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W213);
not MGM_G264(MGM_W214,D);
and MGM_G265(MGM_W215,RN,MGM_W214);
and MGM_G266(MGM_W216,SE,MGM_W215);
not MGM_G267(MGM_W217,SI);
and MGM_G268(ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W217,MGM_W216);
and MGM_G269(MGM_W218,RN,D);
and MGM_G270(MGM_W219,SE,MGM_W218);
not MGM_G271(MGM_W220,SI);
and MGM_G272(ENABLE_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W220,MGM_W219);
not MGM_G273(MGM_W221,CLK);
not MGM_G274(MGM_W222,D);
and MGM_G275(MGM_W223,MGM_W222,MGM_W221);
and MGM_G276(MGM_W224,RN,MGM_W223);
not MGM_G277(MGM_W225,SE);
and MGM_G278(MGM_W226,MGM_W225,MGM_W224);
not MGM_G279(MGM_W227,SI);
and MGM_G280(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W227,MGM_W226);
not MGM_G281(MGM_W228,CLK);
not MGM_G282(MGM_W229,D);
and MGM_G283(MGM_W230,MGM_W229,MGM_W228);
and MGM_G284(MGM_W231,RN,MGM_W230);
not MGM_G285(MGM_W232,SE);
and MGM_G286(MGM_W233,MGM_W232,MGM_W231);
and MGM_G287(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W233);
not MGM_G288(MGM_W234,CLK);
not MGM_G289(MGM_W235,D);
and MGM_G290(MGM_W236,MGM_W235,MGM_W234);
and MGM_G291(MGM_W237,RN,MGM_W236);
and MGM_G292(MGM_W238,SE,MGM_W237);
not MGM_G293(MGM_W239,SI);
and MGM_G294(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W239,MGM_W238);
not MGM_G295(MGM_W240,CLK);
not MGM_G296(MGM_W241,D);
and MGM_G297(MGM_W242,MGM_W241,MGM_W240);
and MGM_G298(MGM_W243,RN,MGM_W242);
and MGM_G299(MGM_W244,SE,MGM_W243);
and MGM_G300(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W244);
not MGM_G301(MGM_W245,CLK);
and MGM_G302(MGM_W246,D,MGM_W245);
and MGM_G303(MGM_W247,RN,MGM_W246);
not MGM_G304(MGM_W248,SE);
and MGM_G305(MGM_W249,MGM_W248,MGM_W247);
not MGM_G306(MGM_W250,SI);
and MGM_G307(ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W250,MGM_W249);
not MGM_G308(MGM_W251,CLK);
and MGM_G309(MGM_W252,D,MGM_W251);
and MGM_G310(MGM_W253,RN,MGM_W252);
not MGM_G311(MGM_W254,SE);
and MGM_G312(MGM_W255,MGM_W254,MGM_W253);
and MGM_G313(ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W255);
not MGM_G314(MGM_W256,CLK);
and MGM_G315(MGM_W257,D,MGM_W256);
and MGM_G316(MGM_W258,RN,MGM_W257);
and MGM_G317(MGM_W259,SE,MGM_W258);
not MGM_G318(MGM_W260,SI);
and MGM_G319(ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W260,MGM_W259);
not MGM_G320(MGM_W261,CLK);
and MGM_G321(MGM_W262,D,MGM_W261);
and MGM_G322(MGM_W263,RN,MGM_W262);
and MGM_G323(MGM_W264,SE,MGM_W263);
and MGM_G324(ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_SI,SI,MGM_W264);
not MGM_G325(MGM_W265,D);
and MGM_G326(MGM_W266,MGM_W265,CLK);
and MGM_G327(MGM_W267,RN,MGM_W266);
not MGM_G328(MGM_W268,SE);
and MGM_G329(MGM_W269,MGM_W268,MGM_W267);
not MGM_G330(MGM_W270,SI);
and MGM_G331(ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W270,MGM_W269);
not MGM_G332(MGM_W271,D);
and MGM_G333(MGM_W272,MGM_W271,CLK);
and MGM_G334(MGM_W273,RN,MGM_W272);
not MGM_G335(MGM_W274,SE);
and MGM_G336(MGM_W275,MGM_W274,MGM_W273);
and MGM_G337(ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W275);
not MGM_G338(MGM_W276,D);
and MGM_G339(MGM_W277,MGM_W276,CLK);
and MGM_G340(MGM_W278,RN,MGM_W277);
and MGM_G341(MGM_W279,SE,MGM_W278);
not MGM_G342(MGM_W280,SI);
and MGM_G343(ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W280,MGM_W279);
not MGM_G344(MGM_W281,D);
and MGM_G345(MGM_W282,MGM_W281,CLK);
and MGM_G346(MGM_W283,RN,MGM_W282);
and MGM_G347(MGM_W284,SE,MGM_W283);
and MGM_G348(ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W284);
and MGM_G349(MGM_W285,D,CLK);
and MGM_G350(MGM_W286,RN,MGM_W285);
not MGM_G351(MGM_W287,SE);
and MGM_G352(MGM_W288,MGM_W287,MGM_W286);
not MGM_G353(MGM_W289,SI);
and MGM_G354(ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W289,MGM_W288);
and MGM_G355(MGM_W290,D,CLK);
and MGM_G356(MGM_W291,RN,MGM_W290);
not MGM_G357(MGM_W292,SE);
and MGM_G358(MGM_W293,MGM_W292,MGM_W291);
and MGM_G359(ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W293);
and MGM_G360(MGM_W294,D,CLK);
and MGM_G361(MGM_W295,RN,MGM_W294);
and MGM_G362(MGM_W296,SE,MGM_W295);
not MGM_G363(MGM_W297,SI);
and MGM_G364(ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W297,MGM_W296);
and MGM_G365(MGM_W298,D,CLK);
and MGM_G366(MGM_W299,RN,MGM_W298);
and MGM_G367(MGM_W300,SE,MGM_W299);
and MGM_G368(ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_SI,SI,MGM_W300);
not MGM_G369(MGM_W301,D);
and MGM_G370(MGM_W302,RN,MGM_W301);
and MGM_G371(MGM_W303,SE,MGM_W302);
and MGM_G372(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN,SETN,MGM_W303);
and MGM_G373(MGM_W304,RN,D);
and MGM_G374(MGM_W305,SE,MGM_W304);
and MGM_G375(ENABLE_D_AND_RN_AND_SE_AND_SETN,SETN,MGM_W305);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFRSNQ_X4( SE, SI, D, CLK, SETN, RN, Q );
input CLK, D, RN, SE, SETN, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFRSNQ_X4_func SDFFRSNQ_X4_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
`else
SDFFRSNQ_X4_func SDFFRSNQ_X4_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.RN(RN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
and MGM_G1(MGM_W1,RN,MGM_W0);
not MGM_G2(MGM_W2,SE);
and MGM_G3(MGM_W3,MGM_W2,MGM_W1);
and MGM_G4(MGM_W4,SETN,MGM_W3);
not MGM_G5(MGM_W5,SI);
and MGM_G6(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W5,MGM_W4);
not MGM_G7(MGM_W6,D);
and MGM_G8(MGM_W7,RN,MGM_W6);
not MGM_G9(MGM_W8,SE);
and MGM_G10(MGM_W9,MGM_W8,MGM_W7);
and MGM_G11(MGM_W10,SETN,MGM_W9);
and MGM_G12(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W10);
not MGM_G13(MGM_W11,D);
and MGM_G14(MGM_W12,RN,MGM_W11);
and MGM_G15(MGM_W13,SE,MGM_W12);
and MGM_G16(MGM_W14,SETN,MGM_W13);
not MGM_G17(MGM_W15,SI);
and MGM_G18(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI,MGM_W15,MGM_W14);
not MGM_G19(MGM_W16,D);
and MGM_G20(MGM_W17,RN,MGM_W16);
and MGM_G21(MGM_W18,SE,MGM_W17);
and MGM_G22(MGM_W19,SETN,MGM_W18);
and MGM_G23(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI,SI,MGM_W19);
and MGM_G24(MGM_W20,RN,D);
not MGM_G25(MGM_W21,SE);
and MGM_G26(MGM_W22,MGM_W21,MGM_W20);
and MGM_G27(MGM_W23,SETN,MGM_W22);
not MGM_G28(MGM_W24,SI);
and MGM_G29(ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W24,MGM_W23);
and MGM_G30(MGM_W25,RN,D);
not MGM_G31(MGM_W26,SE);
and MGM_G32(MGM_W27,MGM_W26,MGM_W25);
and MGM_G33(MGM_W28,SETN,MGM_W27);
and MGM_G34(ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W28);
and MGM_G35(MGM_W29,RN,D);
and MGM_G36(MGM_W30,SE,MGM_W29);
and MGM_G37(MGM_W31,SETN,MGM_W30);
not MGM_G38(MGM_W32,SI);
and MGM_G39(ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI,MGM_W32,MGM_W31);
and MGM_G40(MGM_W33,RN,D);
and MGM_G41(MGM_W34,SE,MGM_W33);
and MGM_G42(MGM_W35,SETN,MGM_W34);
and MGM_G43(ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI,SI,MGM_W35);
not MGM_G44(MGM_W36,SE);
and MGM_G45(MGM_W37,MGM_W36,RN);
and MGM_G46(MGM_W38,SETN,MGM_W37);
not MGM_G47(MGM_W39,SI);
and MGM_G48(ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W39,MGM_W38);
not MGM_G49(MGM_W40,SE);
and MGM_G50(MGM_W41,MGM_W40,RN);
and MGM_G51(MGM_W42,SETN,MGM_W41);
and MGM_G52(ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W42);
not MGM_G53(MGM_W43,D);
and MGM_G54(MGM_W44,SE,MGM_W43);
and MGM_G55(MGM_W45,SETN,MGM_W44);
and MGM_G56(ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W45);
not MGM_G57(MGM_W46,SE);
and MGM_G58(MGM_W47,MGM_W46,D);
and MGM_G59(MGM_W48,SETN,MGM_W47);
not MGM_G60(MGM_W49,SI);
and MGM_G61(ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W49,MGM_W48);
not MGM_G62(MGM_W50,SE);
and MGM_G63(MGM_W51,MGM_W50,D);
and MGM_G64(MGM_W52,SETN,MGM_W51);
and MGM_G65(ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W52);
and MGM_G66(MGM_W53,SE,D);
and MGM_G67(MGM_W54,SETN,MGM_W53);
and MGM_G68(ENABLE_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W54);
not MGM_G69(MGM_W55,CLK);
not MGM_G70(MGM_W56,D);
and MGM_G71(MGM_W57,MGM_W56,MGM_W55);
not MGM_G72(MGM_W58,SE);
and MGM_G73(MGM_W59,MGM_W58,MGM_W57);
and MGM_G74(MGM_W60,SETN,MGM_W59);
not MGM_G75(MGM_W61,SI);
and MGM_G76(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W61,MGM_W60);
not MGM_G77(MGM_W62,CLK);
not MGM_G78(MGM_W63,D);
and MGM_G79(MGM_W64,MGM_W63,MGM_W62);
not MGM_G80(MGM_W65,SE);
and MGM_G81(MGM_W66,MGM_W65,MGM_W64);
and MGM_G82(MGM_W67,SETN,MGM_W66);
and MGM_G83(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W67);
not MGM_G84(MGM_W68,CLK);
not MGM_G85(MGM_W69,D);
and MGM_G86(MGM_W70,MGM_W69,MGM_W68);
and MGM_G87(MGM_W71,SE,MGM_W70);
and MGM_G88(MGM_W72,SETN,MGM_W71);
not MGM_G89(MGM_W73,SI);
and MGM_G90(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G91(MGM_W74,CLK);
not MGM_G92(MGM_W75,D);
and MGM_G93(MGM_W76,MGM_W75,MGM_W74);
and MGM_G94(MGM_W77,SE,MGM_W76);
and MGM_G95(MGM_W78,SETN,MGM_W77);
and MGM_G96(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W78);
not MGM_G97(MGM_W79,CLK);
and MGM_G98(MGM_W80,D,MGM_W79);
not MGM_G99(MGM_W81,SE);
and MGM_G100(MGM_W82,MGM_W81,MGM_W80);
and MGM_G101(MGM_W83,SETN,MGM_W82);
not MGM_G102(MGM_W84,SI);
and MGM_G103(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W84,MGM_W83);
not MGM_G104(MGM_W85,CLK);
and MGM_G105(MGM_W86,D,MGM_W85);
not MGM_G106(MGM_W87,SE);
and MGM_G107(MGM_W88,MGM_W87,MGM_W86);
and MGM_G108(MGM_W89,SETN,MGM_W88);
and MGM_G109(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W89);
not MGM_G110(MGM_W90,CLK);
and MGM_G111(MGM_W91,D,MGM_W90);
and MGM_G112(MGM_W92,SE,MGM_W91);
and MGM_G113(MGM_W93,SETN,MGM_W92);
not MGM_G114(MGM_W94,SI);
and MGM_G115(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W94,MGM_W93);
not MGM_G116(MGM_W95,CLK);
and MGM_G117(MGM_W96,D,MGM_W95);
and MGM_G118(MGM_W97,SE,MGM_W96);
and MGM_G119(MGM_W98,SETN,MGM_W97);
and MGM_G120(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W98);
not MGM_G121(MGM_W99,D);
and MGM_G122(MGM_W100,MGM_W99,CLK);
not MGM_G123(MGM_W101,SE);
and MGM_G124(MGM_W102,MGM_W101,MGM_W100);
and MGM_G125(MGM_W103,SETN,MGM_W102);
not MGM_G126(MGM_W104,SI);
and MGM_G127(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W104,MGM_W103);
not MGM_G128(MGM_W105,D);
and MGM_G129(MGM_W106,MGM_W105,CLK);
not MGM_G130(MGM_W107,SE);
and MGM_G131(MGM_W108,MGM_W107,MGM_W106);
and MGM_G132(MGM_W109,SETN,MGM_W108);
and MGM_G133(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W109);
not MGM_G134(MGM_W110,D);
and MGM_G135(MGM_W111,MGM_W110,CLK);
and MGM_G136(MGM_W112,SE,MGM_W111);
and MGM_G137(MGM_W113,SETN,MGM_W112);
not MGM_G138(MGM_W114,SI);
and MGM_G139(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W114,MGM_W113);
not MGM_G140(MGM_W115,D);
and MGM_G141(MGM_W116,MGM_W115,CLK);
and MGM_G142(MGM_W117,SE,MGM_W116);
and MGM_G143(MGM_W118,SETN,MGM_W117);
and MGM_G144(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W118);
and MGM_G145(MGM_W119,D,CLK);
not MGM_G146(MGM_W120,SE);
and MGM_G147(MGM_W121,MGM_W120,MGM_W119);
and MGM_G148(MGM_W122,SETN,MGM_W121);
not MGM_G149(MGM_W123,SI);
and MGM_G150(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W123,MGM_W122);
and MGM_G151(MGM_W124,D,CLK);
not MGM_G152(MGM_W125,SE);
and MGM_G153(MGM_W126,MGM_W125,MGM_W124);
and MGM_G154(MGM_W127,SETN,MGM_W126);
and MGM_G155(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W127);
and MGM_G156(MGM_W128,D,CLK);
and MGM_G157(MGM_W129,SE,MGM_W128);
and MGM_G158(MGM_W130,SETN,MGM_W129);
not MGM_G159(MGM_W131,SI);
and MGM_G160(ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W131,MGM_W130);
and MGM_G161(MGM_W132,D,CLK);
and MGM_G162(MGM_W133,SE,MGM_W132);
and MGM_G163(MGM_W134,SETN,MGM_W133);
and MGM_G164(ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W134);
not MGM_G165(MGM_W135,CLK);
not MGM_G166(MGM_W136,D);
and MGM_G167(MGM_W137,MGM_W136,MGM_W135);
not MGM_G168(MGM_W138,SE);
and MGM_G169(MGM_W139,MGM_W138,MGM_W137);
not MGM_G170(MGM_W140,SI);
and MGM_G171(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W140,MGM_W139);
not MGM_G172(MGM_W141,CLK);
not MGM_G173(MGM_W142,D);
and MGM_G174(MGM_W143,MGM_W142,MGM_W141);
not MGM_G175(MGM_W144,SE);
and MGM_G176(MGM_W145,MGM_W144,MGM_W143);
and MGM_G177(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W145);
not MGM_G178(MGM_W146,CLK);
not MGM_G179(MGM_W147,D);
and MGM_G180(MGM_W148,MGM_W147,MGM_W146);
and MGM_G181(MGM_W149,SE,MGM_W148);
not MGM_G182(MGM_W150,SI);
and MGM_G183(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W150,MGM_W149);
not MGM_G184(MGM_W151,CLK);
not MGM_G185(MGM_W152,D);
and MGM_G186(MGM_W153,MGM_W152,MGM_W151);
and MGM_G187(MGM_W154,SE,MGM_W153);
and MGM_G188(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W154);
not MGM_G189(MGM_W155,CLK);
and MGM_G190(MGM_W156,D,MGM_W155);
not MGM_G191(MGM_W157,SE);
and MGM_G192(MGM_W158,MGM_W157,MGM_W156);
not MGM_G193(MGM_W159,SI);
and MGM_G194(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W159,MGM_W158);
not MGM_G195(MGM_W160,CLK);
and MGM_G196(MGM_W161,D,MGM_W160);
not MGM_G197(MGM_W162,SE);
and MGM_G198(MGM_W163,MGM_W162,MGM_W161);
and MGM_G199(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W163);
not MGM_G200(MGM_W164,CLK);
and MGM_G201(MGM_W165,D,MGM_W164);
and MGM_G202(MGM_W166,SE,MGM_W165);
not MGM_G203(MGM_W167,SI);
and MGM_G204(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W167,MGM_W166);
not MGM_G205(MGM_W168,CLK);
and MGM_G206(MGM_W169,D,MGM_W168);
and MGM_G207(MGM_W170,SE,MGM_W169);
and MGM_G208(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W170);
not MGM_G209(MGM_W171,D);
and MGM_G210(MGM_W172,MGM_W171,CLK);
not MGM_G211(MGM_W173,SE);
and MGM_G212(MGM_W174,MGM_W173,MGM_W172);
not MGM_G213(MGM_W175,SI);
and MGM_G214(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W175,MGM_W174);
not MGM_G215(MGM_W176,D);
and MGM_G216(MGM_W177,MGM_W176,CLK);
not MGM_G217(MGM_W178,SE);
and MGM_G218(MGM_W179,MGM_W178,MGM_W177);
and MGM_G219(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W179);
not MGM_G220(MGM_W180,D);
and MGM_G221(MGM_W181,MGM_W180,CLK);
and MGM_G222(MGM_W182,SE,MGM_W181);
not MGM_G223(MGM_W183,SI);
and MGM_G224(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W183,MGM_W182);
not MGM_G225(MGM_W184,D);
and MGM_G226(MGM_W185,MGM_W184,CLK);
and MGM_G227(MGM_W186,SE,MGM_W185);
and MGM_G228(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W186);
and MGM_G229(MGM_W187,D,CLK);
not MGM_G230(MGM_W188,SE);
and MGM_G231(MGM_W189,MGM_W188,MGM_W187);
not MGM_G232(MGM_W190,SI);
and MGM_G233(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W190,MGM_W189);
and MGM_G234(MGM_W191,D,CLK);
not MGM_G235(MGM_W192,SE);
and MGM_G236(MGM_W193,MGM_W192,MGM_W191);
and MGM_G237(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W193);
and MGM_G238(MGM_W194,D,CLK);
and MGM_G239(MGM_W195,SE,MGM_W194);
not MGM_G240(MGM_W196,SI);
and MGM_G241(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W196,MGM_W195);
and MGM_G242(MGM_W197,D,CLK);
and MGM_G243(MGM_W198,SE,MGM_W197);
and MGM_G244(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W198);
not MGM_G245(MGM_W199,D);
and MGM_G246(MGM_W200,RN,MGM_W199);
and MGM_G247(MGM_W201,SETN,MGM_W200);
and MGM_G248(ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI,SI,MGM_W201);
and MGM_G249(MGM_W202,RN,D);
and MGM_G250(MGM_W203,SETN,MGM_W202);
not MGM_G251(MGM_W204,SI);
and MGM_G252(ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI,MGM_W204,MGM_W203);
not MGM_G253(MGM_W205,D);
and MGM_G254(MGM_W206,RN,MGM_W205);
not MGM_G255(MGM_W207,SE);
and MGM_G256(MGM_W208,MGM_W207,MGM_W206);
not MGM_G257(MGM_W209,SI);
and MGM_G258(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W209,MGM_W208);
not MGM_G259(MGM_W210,D);
and MGM_G260(MGM_W211,RN,MGM_W210);
not MGM_G261(MGM_W212,SE);
and MGM_G262(MGM_W213,MGM_W212,MGM_W211);
and MGM_G263(ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W213);
not MGM_G264(MGM_W214,D);
and MGM_G265(MGM_W215,RN,MGM_W214);
and MGM_G266(MGM_W216,SE,MGM_W215);
not MGM_G267(MGM_W217,SI);
and MGM_G268(ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W217,MGM_W216);
and MGM_G269(MGM_W218,RN,D);
and MGM_G270(MGM_W219,SE,MGM_W218);
not MGM_G271(MGM_W220,SI);
and MGM_G272(ENABLE_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W220,MGM_W219);
not MGM_G273(MGM_W221,CLK);
not MGM_G274(MGM_W222,D);
and MGM_G275(MGM_W223,MGM_W222,MGM_W221);
and MGM_G276(MGM_W224,RN,MGM_W223);
not MGM_G277(MGM_W225,SE);
and MGM_G278(MGM_W226,MGM_W225,MGM_W224);
not MGM_G279(MGM_W227,SI);
and MGM_G280(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W227,MGM_W226);
not MGM_G281(MGM_W228,CLK);
not MGM_G282(MGM_W229,D);
and MGM_G283(MGM_W230,MGM_W229,MGM_W228);
and MGM_G284(MGM_W231,RN,MGM_W230);
not MGM_G285(MGM_W232,SE);
and MGM_G286(MGM_W233,MGM_W232,MGM_W231);
and MGM_G287(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W233);
not MGM_G288(MGM_W234,CLK);
not MGM_G289(MGM_W235,D);
and MGM_G290(MGM_W236,MGM_W235,MGM_W234);
and MGM_G291(MGM_W237,RN,MGM_W236);
and MGM_G292(MGM_W238,SE,MGM_W237);
not MGM_G293(MGM_W239,SI);
and MGM_G294(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W239,MGM_W238);
not MGM_G295(MGM_W240,CLK);
not MGM_G296(MGM_W241,D);
and MGM_G297(MGM_W242,MGM_W241,MGM_W240);
and MGM_G298(MGM_W243,RN,MGM_W242);
and MGM_G299(MGM_W244,SE,MGM_W243);
and MGM_G300(ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W244);
not MGM_G301(MGM_W245,CLK);
and MGM_G302(MGM_W246,D,MGM_W245);
and MGM_G303(MGM_W247,RN,MGM_W246);
not MGM_G304(MGM_W248,SE);
and MGM_G305(MGM_W249,MGM_W248,MGM_W247);
not MGM_G306(MGM_W250,SI);
and MGM_G307(ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W250,MGM_W249);
not MGM_G308(MGM_W251,CLK);
and MGM_G309(MGM_W252,D,MGM_W251);
and MGM_G310(MGM_W253,RN,MGM_W252);
not MGM_G311(MGM_W254,SE);
and MGM_G312(MGM_W255,MGM_W254,MGM_W253);
and MGM_G313(ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W255);
not MGM_G314(MGM_W256,CLK);
and MGM_G315(MGM_W257,D,MGM_W256);
and MGM_G316(MGM_W258,RN,MGM_W257);
and MGM_G317(MGM_W259,SE,MGM_W258);
not MGM_G318(MGM_W260,SI);
and MGM_G319(ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W260,MGM_W259);
not MGM_G320(MGM_W261,CLK);
and MGM_G321(MGM_W262,D,MGM_W261);
and MGM_G322(MGM_W263,RN,MGM_W262);
and MGM_G323(MGM_W264,SE,MGM_W263);
and MGM_G324(ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_SI,SI,MGM_W264);
not MGM_G325(MGM_W265,D);
and MGM_G326(MGM_W266,MGM_W265,CLK);
and MGM_G327(MGM_W267,RN,MGM_W266);
not MGM_G328(MGM_W268,SE);
and MGM_G329(MGM_W269,MGM_W268,MGM_W267);
not MGM_G330(MGM_W270,SI);
and MGM_G331(ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W270,MGM_W269);
not MGM_G332(MGM_W271,D);
and MGM_G333(MGM_W272,MGM_W271,CLK);
and MGM_G334(MGM_W273,RN,MGM_W272);
not MGM_G335(MGM_W274,SE);
and MGM_G336(MGM_W275,MGM_W274,MGM_W273);
and MGM_G337(ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W275);
not MGM_G338(MGM_W276,D);
and MGM_G339(MGM_W277,MGM_W276,CLK);
and MGM_G340(MGM_W278,RN,MGM_W277);
and MGM_G341(MGM_W279,SE,MGM_W278);
not MGM_G342(MGM_W280,SI);
and MGM_G343(ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W280,MGM_W279);
not MGM_G344(MGM_W281,D);
and MGM_G345(MGM_W282,MGM_W281,CLK);
and MGM_G346(MGM_W283,RN,MGM_W282);
and MGM_G347(MGM_W284,SE,MGM_W283);
and MGM_G348(ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI,SI,MGM_W284);
and MGM_G349(MGM_W285,D,CLK);
and MGM_G350(MGM_W286,RN,MGM_W285);
not MGM_G351(MGM_W287,SE);
and MGM_G352(MGM_W288,MGM_W287,MGM_W286);
not MGM_G353(MGM_W289,SI);
and MGM_G354(ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI,MGM_W289,MGM_W288);
and MGM_G355(MGM_W290,D,CLK);
and MGM_G356(MGM_W291,RN,MGM_W290);
not MGM_G357(MGM_W292,SE);
and MGM_G358(MGM_W293,MGM_W292,MGM_W291);
and MGM_G359(ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI,SI,MGM_W293);
and MGM_G360(MGM_W294,D,CLK);
and MGM_G361(MGM_W295,RN,MGM_W294);
and MGM_G362(MGM_W296,SE,MGM_W295);
not MGM_G363(MGM_W297,SI);
and MGM_G364(ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI,MGM_W297,MGM_W296);
and MGM_G365(MGM_W298,D,CLK);
and MGM_G366(MGM_W299,RN,MGM_W298);
and MGM_G367(MGM_W300,SE,MGM_W299);
and MGM_G368(ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_SI,SI,MGM_W300);
not MGM_G369(MGM_W301,D);
and MGM_G370(MGM_W302,RN,MGM_W301);
and MGM_G371(MGM_W303,SE,MGM_W302);
and MGM_G372(ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN,SETN,MGM_W303);
and MGM_G373(MGM_W304,RN,D);
and MGM_G374(MGM_W305,SE,MGM_W304);
and MGM_G375(ENABLE_D_AND_RN_AND_SE_AND_SETN,SETN,MGM_W305);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b0 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b0)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SETN===1'b1 && SI===1'b1)
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
ifnone
// seq arc RN --> Q
(RN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// recovery RN-LH CLK-LH
$recovery(posedge RN &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// removal RN-LH CLK-LH
$removal(posedge RN &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold RN-LH SETN-LH
$hold(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup RN-LH SETN-LH
$setup(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SETN-LH RN-LH
$hold(posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
// setup SETN-LH RN-LH
$setup(posedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),
posedge RN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_RN_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw RN_hl
$width(negedge RN,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_RN_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFSNQ_X1( SE, SI, D, CLK, SETN, Q );
input CLK, D, SE, SETN, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFSNQ_X1_func SDFFSNQ_X1_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
SDFFSNQ_X1_func SDFFSNQ_X1_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
not MGM_G1(MGM_W1,SE);
and MGM_G2(MGM_W2,MGM_W1,MGM_W0);
and MGM_G3(MGM_W3,SETN,MGM_W2);
not MGM_G4(MGM_W4,SI);
and MGM_G5(ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W4,MGM_W3);
not MGM_G6(MGM_W5,D);
not MGM_G7(MGM_W6,SE);
and MGM_G8(MGM_W7,MGM_W6,MGM_W5);
and MGM_G9(MGM_W8,SETN,MGM_W7);
and MGM_G10(ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W8);
not MGM_G11(MGM_W9,D);
and MGM_G12(MGM_W10,SE,MGM_W9);
and MGM_G13(MGM_W11,SETN,MGM_W10);
not MGM_G14(MGM_W12,SI);
and MGM_G15(ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W12,MGM_W11);
not MGM_G16(MGM_W13,D);
and MGM_G17(MGM_W14,SE,MGM_W13);
and MGM_G18(MGM_W15,SETN,MGM_W14);
and MGM_G19(ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W15);
not MGM_G20(MGM_W16,SE);
and MGM_G21(MGM_W17,MGM_W16,D);
and MGM_G22(MGM_W18,SETN,MGM_W17);
not MGM_G23(MGM_W19,SI);
and MGM_G24(ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W19,MGM_W18);
not MGM_G25(MGM_W20,SE);
and MGM_G26(MGM_W21,MGM_W20,D);
and MGM_G27(MGM_W22,SETN,MGM_W21);
and MGM_G28(ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W22);
and MGM_G29(MGM_W23,SE,D);
and MGM_G30(MGM_W24,SETN,MGM_W23);
not MGM_G31(MGM_W25,SI);
and MGM_G32(ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W25,MGM_W24);
and MGM_G33(MGM_W26,SE,D);
and MGM_G34(MGM_W27,SETN,MGM_W26);
and MGM_G35(ENABLE_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W27);
not MGM_G36(MGM_W28,SE);
and MGM_G37(MGM_W29,SETN,MGM_W28);
not MGM_G38(MGM_W30,SI);
and MGM_G39(ENABLE_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W30,MGM_W29);
not MGM_G40(MGM_W31,SE);
and MGM_G41(MGM_W32,SETN,MGM_W31);
and MGM_G42(ENABLE_NOT_SE_AND_SETN_AND_SI,SI,MGM_W32);
not MGM_G43(MGM_W33,D);
and MGM_G44(MGM_W34,SETN,MGM_W33);
and MGM_G45(ENABLE_NOT_D_AND_SETN_AND_SI,SI,MGM_W34);
and MGM_G46(MGM_W35,SETN,D);
not MGM_G47(MGM_W36,SI);
and MGM_G48(ENABLE_D_AND_SETN_AND_NOT_SI,MGM_W36,MGM_W35);
not MGM_G49(MGM_W37,D);
not MGM_G50(MGM_W38,SE);
and MGM_G51(MGM_W39,MGM_W38,MGM_W37);
not MGM_G52(MGM_W40,SI);
and MGM_G53(ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W40,MGM_W39);
not MGM_G54(MGM_W41,D);
not MGM_G55(MGM_W42,SE);
and MGM_G56(MGM_W43,MGM_W42,MGM_W41);
and MGM_G57(ENABLE_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W43);
not MGM_G58(MGM_W44,D);
and MGM_G59(MGM_W45,SE,MGM_W44);
not MGM_G60(MGM_W46,SI);
and MGM_G61(ENABLE_NOT_D_AND_SE_AND_NOT_SI,MGM_W46,MGM_W45);
and MGM_G62(MGM_W47,SE,D);
not MGM_G63(MGM_W48,SI);
and MGM_G64(ENABLE_D_AND_SE_AND_NOT_SI,MGM_W48,MGM_W47);
not MGM_G65(MGM_W49,CLK);
not MGM_G66(MGM_W50,D);
and MGM_G67(MGM_W51,MGM_W50,MGM_W49);
not MGM_G68(MGM_W52,SE);
and MGM_G69(MGM_W53,MGM_W52,MGM_W51);
not MGM_G70(MGM_W54,SI);
and MGM_G71(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W54,MGM_W53);
not MGM_G72(MGM_W55,CLK);
not MGM_G73(MGM_W56,D);
and MGM_G74(MGM_W57,MGM_W56,MGM_W55);
not MGM_G75(MGM_W58,SE);
and MGM_G76(MGM_W59,MGM_W58,MGM_W57);
and MGM_G77(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W59);
not MGM_G78(MGM_W60,CLK);
not MGM_G79(MGM_W61,D);
and MGM_G80(MGM_W62,MGM_W61,MGM_W60);
and MGM_G81(MGM_W63,SE,MGM_W62);
not MGM_G82(MGM_W64,SI);
and MGM_G83(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W64,MGM_W63);
not MGM_G84(MGM_W65,CLK);
not MGM_G85(MGM_W66,D);
and MGM_G86(MGM_W67,MGM_W66,MGM_W65);
and MGM_G87(MGM_W68,SE,MGM_W67);
and MGM_G88(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W68);
not MGM_G89(MGM_W69,CLK);
and MGM_G90(MGM_W70,D,MGM_W69);
not MGM_G91(MGM_W71,SE);
and MGM_G92(MGM_W72,MGM_W71,MGM_W70);
not MGM_G93(MGM_W73,SI);
and MGM_G94(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G95(MGM_W74,CLK);
and MGM_G96(MGM_W75,D,MGM_W74);
not MGM_G97(MGM_W76,SE);
and MGM_G98(MGM_W77,MGM_W76,MGM_W75);
and MGM_G99(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W77);
not MGM_G100(MGM_W78,CLK);
and MGM_G101(MGM_W79,D,MGM_W78);
and MGM_G102(MGM_W80,SE,MGM_W79);
not MGM_G103(MGM_W81,SI);
and MGM_G104(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W81,MGM_W80);
not MGM_G105(MGM_W82,CLK);
and MGM_G106(MGM_W83,D,MGM_W82);
and MGM_G107(MGM_W84,SE,MGM_W83);
and MGM_G108(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W84);
not MGM_G109(MGM_W85,D);
and MGM_G110(MGM_W86,MGM_W85,CLK);
not MGM_G111(MGM_W87,SE);
and MGM_G112(MGM_W88,MGM_W87,MGM_W86);
not MGM_G113(MGM_W89,SI);
and MGM_G114(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W89,MGM_W88);
not MGM_G115(MGM_W90,D);
and MGM_G116(MGM_W91,MGM_W90,CLK);
not MGM_G117(MGM_W92,SE);
and MGM_G118(MGM_W93,MGM_W92,MGM_W91);
and MGM_G119(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W93);
not MGM_G120(MGM_W94,D);
and MGM_G121(MGM_W95,MGM_W94,CLK);
and MGM_G122(MGM_W96,SE,MGM_W95);
not MGM_G123(MGM_W97,SI);
and MGM_G124(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W97,MGM_W96);
not MGM_G125(MGM_W98,D);
and MGM_G126(MGM_W99,MGM_W98,CLK);
and MGM_G127(MGM_W100,SE,MGM_W99);
and MGM_G128(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W100);
and MGM_G129(MGM_W101,D,CLK);
not MGM_G130(MGM_W102,SE);
and MGM_G131(MGM_W103,MGM_W102,MGM_W101);
not MGM_G132(MGM_W104,SI);
and MGM_G133(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W104,MGM_W103);
and MGM_G134(MGM_W105,D,CLK);
not MGM_G135(MGM_W106,SE);
and MGM_G136(MGM_W107,MGM_W106,MGM_W105);
and MGM_G137(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W107);
and MGM_G138(MGM_W108,D,CLK);
and MGM_G139(MGM_W109,SE,MGM_W108);
not MGM_G140(MGM_W110,SI);
and MGM_G141(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W110,MGM_W109);
and MGM_G142(MGM_W111,D,CLK);
and MGM_G143(MGM_W112,SE,MGM_W111);
and MGM_G144(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W112);
not MGM_G145(MGM_W113,D);
and MGM_G146(MGM_W114,SE,MGM_W113);
and MGM_G147(ENABLE_NOT_D_AND_SE_AND_SETN,SETN,MGM_W114);
and MGM_G148(MGM_W115,SE,D);
and MGM_G149(ENABLE_D_AND_SE_AND_SETN,SETN,MGM_W115);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFSNQ_X2( SE, SI, D, CLK, SETN, Q );
input CLK, D, SE, SETN, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFSNQ_X2_func SDFFSNQ_X2_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
SDFFSNQ_X2_func SDFFSNQ_X2_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
not MGM_G1(MGM_W1,SE);
and MGM_G2(MGM_W2,MGM_W1,MGM_W0);
and MGM_G3(MGM_W3,SETN,MGM_W2);
not MGM_G4(MGM_W4,SI);
and MGM_G5(ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W4,MGM_W3);
not MGM_G6(MGM_W5,D);
not MGM_G7(MGM_W6,SE);
and MGM_G8(MGM_W7,MGM_W6,MGM_W5);
and MGM_G9(MGM_W8,SETN,MGM_W7);
and MGM_G10(ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W8);
not MGM_G11(MGM_W9,D);
and MGM_G12(MGM_W10,SE,MGM_W9);
and MGM_G13(MGM_W11,SETN,MGM_W10);
not MGM_G14(MGM_W12,SI);
and MGM_G15(ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W12,MGM_W11);
not MGM_G16(MGM_W13,D);
and MGM_G17(MGM_W14,SE,MGM_W13);
and MGM_G18(MGM_W15,SETN,MGM_W14);
and MGM_G19(ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W15);
not MGM_G20(MGM_W16,SE);
and MGM_G21(MGM_W17,MGM_W16,D);
and MGM_G22(MGM_W18,SETN,MGM_W17);
not MGM_G23(MGM_W19,SI);
and MGM_G24(ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W19,MGM_W18);
not MGM_G25(MGM_W20,SE);
and MGM_G26(MGM_W21,MGM_W20,D);
and MGM_G27(MGM_W22,SETN,MGM_W21);
and MGM_G28(ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W22);
and MGM_G29(MGM_W23,SE,D);
and MGM_G30(MGM_W24,SETN,MGM_W23);
not MGM_G31(MGM_W25,SI);
and MGM_G32(ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W25,MGM_W24);
and MGM_G33(MGM_W26,SE,D);
and MGM_G34(MGM_W27,SETN,MGM_W26);
and MGM_G35(ENABLE_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W27);
not MGM_G36(MGM_W28,SE);
and MGM_G37(MGM_W29,SETN,MGM_W28);
not MGM_G38(MGM_W30,SI);
and MGM_G39(ENABLE_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W30,MGM_W29);
not MGM_G40(MGM_W31,SE);
and MGM_G41(MGM_W32,SETN,MGM_W31);
and MGM_G42(ENABLE_NOT_SE_AND_SETN_AND_SI,SI,MGM_W32);
not MGM_G43(MGM_W33,D);
and MGM_G44(MGM_W34,SETN,MGM_W33);
and MGM_G45(ENABLE_NOT_D_AND_SETN_AND_SI,SI,MGM_W34);
and MGM_G46(MGM_W35,SETN,D);
not MGM_G47(MGM_W36,SI);
and MGM_G48(ENABLE_D_AND_SETN_AND_NOT_SI,MGM_W36,MGM_W35);
not MGM_G49(MGM_W37,D);
not MGM_G50(MGM_W38,SE);
and MGM_G51(MGM_W39,MGM_W38,MGM_W37);
not MGM_G52(MGM_W40,SI);
and MGM_G53(ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W40,MGM_W39);
not MGM_G54(MGM_W41,D);
not MGM_G55(MGM_W42,SE);
and MGM_G56(MGM_W43,MGM_W42,MGM_W41);
and MGM_G57(ENABLE_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W43);
not MGM_G58(MGM_W44,D);
and MGM_G59(MGM_W45,SE,MGM_W44);
not MGM_G60(MGM_W46,SI);
and MGM_G61(ENABLE_NOT_D_AND_SE_AND_NOT_SI,MGM_W46,MGM_W45);
and MGM_G62(MGM_W47,SE,D);
not MGM_G63(MGM_W48,SI);
and MGM_G64(ENABLE_D_AND_SE_AND_NOT_SI,MGM_W48,MGM_W47);
not MGM_G65(MGM_W49,CLK);
not MGM_G66(MGM_W50,D);
and MGM_G67(MGM_W51,MGM_W50,MGM_W49);
not MGM_G68(MGM_W52,SE);
and MGM_G69(MGM_W53,MGM_W52,MGM_W51);
not MGM_G70(MGM_W54,SI);
and MGM_G71(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W54,MGM_W53);
not MGM_G72(MGM_W55,CLK);
not MGM_G73(MGM_W56,D);
and MGM_G74(MGM_W57,MGM_W56,MGM_W55);
not MGM_G75(MGM_W58,SE);
and MGM_G76(MGM_W59,MGM_W58,MGM_W57);
and MGM_G77(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W59);
not MGM_G78(MGM_W60,CLK);
not MGM_G79(MGM_W61,D);
and MGM_G80(MGM_W62,MGM_W61,MGM_W60);
and MGM_G81(MGM_W63,SE,MGM_W62);
not MGM_G82(MGM_W64,SI);
and MGM_G83(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W64,MGM_W63);
not MGM_G84(MGM_W65,CLK);
not MGM_G85(MGM_W66,D);
and MGM_G86(MGM_W67,MGM_W66,MGM_W65);
and MGM_G87(MGM_W68,SE,MGM_W67);
and MGM_G88(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W68);
not MGM_G89(MGM_W69,CLK);
and MGM_G90(MGM_W70,D,MGM_W69);
not MGM_G91(MGM_W71,SE);
and MGM_G92(MGM_W72,MGM_W71,MGM_W70);
not MGM_G93(MGM_W73,SI);
and MGM_G94(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G95(MGM_W74,CLK);
and MGM_G96(MGM_W75,D,MGM_W74);
not MGM_G97(MGM_W76,SE);
and MGM_G98(MGM_W77,MGM_W76,MGM_W75);
and MGM_G99(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W77);
not MGM_G100(MGM_W78,CLK);
and MGM_G101(MGM_W79,D,MGM_W78);
and MGM_G102(MGM_W80,SE,MGM_W79);
not MGM_G103(MGM_W81,SI);
and MGM_G104(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W81,MGM_W80);
not MGM_G105(MGM_W82,CLK);
and MGM_G106(MGM_W83,D,MGM_W82);
and MGM_G107(MGM_W84,SE,MGM_W83);
and MGM_G108(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W84);
not MGM_G109(MGM_W85,D);
and MGM_G110(MGM_W86,MGM_W85,CLK);
not MGM_G111(MGM_W87,SE);
and MGM_G112(MGM_W88,MGM_W87,MGM_W86);
not MGM_G113(MGM_W89,SI);
and MGM_G114(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W89,MGM_W88);
not MGM_G115(MGM_W90,D);
and MGM_G116(MGM_W91,MGM_W90,CLK);
not MGM_G117(MGM_W92,SE);
and MGM_G118(MGM_W93,MGM_W92,MGM_W91);
and MGM_G119(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W93);
not MGM_G120(MGM_W94,D);
and MGM_G121(MGM_W95,MGM_W94,CLK);
and MGM_G122(MGM_W96,SE,MGM_W95);
not MGM_G123(MGM_W97,SI);
and MGM_G124(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W97,MGM_W96);
not MGM_G125(MGM_W98,D);
and MGM_G126(MGM_W99,MGM_W98,CLK);
and MGM_G127(MGM_W100,SE,MGM_W99);
and MGM_G128(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W100);
and MGM_G129(MGM_W101,D,CLK);
not MGM_G130(MGM_W102,SE);
and MGM_G131(MGM_W103,MGM_W102,MGM_W101);
not MGM_G132(MGM_W104,SI);
and MGM_G133(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W104,MGM_W103);
and MGM_G134(MGM_W105,D,CLK);
not MGM_G135(MGM_W106,SE);
and MGM_G136(MGM_W107,MGM_W106,MGM_W105);
and MGM_G137(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W107);
and MGM_G138(MGM_W108,D,CLK);
and MGM_G139(MGM_W109,SE,MGM_W108);
not MGM_G140(MGM_W110,SI);
and MGM_G141(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W110,MGM_W109);
and MGM_G142(MGM_W111,D,CLK);
and MGM_G143(MGM_W112,SE,MGM_W111);
and MGM_G144(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W112);
not MGM_G145(MGM_W113,D);
and MGM_G146(MGM_W114,SE,MGM_W113);
and MGM_G147(ENABLE_NOT_D_AND_SE_AND_SETN,SETN,MGM_W114);
and MGM_G148(MGM_W115,SE,D);
and MGM_G149(ENABLE_D_AND_SE_AND_SETN,SETN,MGM_W115);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module SDFFSNQ_X4( SE, SI, D, CLK, SETN, Q );
input CLK, D, SE, SETN, SI;
output Q;
reg notifier;
`ifdef FUNCTIONAL // functional //
SDFFSNQ_X4_func SDFFSNQ_X4_behav_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.Q(Q),.notifier(notifier));
`else
SDFFSNQ_X4_func SDFFSNQ_X4_inst(.SE(SE),.SI(SI),.D(D),.CLK(CLK),.SETN(SETN),.Q(Q),.notifier(notifier));
// spec_gates_begin
not MGM_G0(MGM_W0,D);
not MGM_G1(MGM_W1,SE);
and MGM_G2(MGM_W2,MGM_W1,MGM_W0);
and MGM_G3(MGM_W3,SETN,MGM_W2);
not MGM_G4(MGM_W4,SI);
and MGM_G5(ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W4,MGM_W3);
not MGM_G6(MGM_W5,D);
not MGM_G7(MGM_W6,SE);
and MGM_G8(MGM_W7,MGM_W6,MGM_W5);
and MGM_G9(MGM_W8,SETN,MGM_W7);
and MGM_G10(ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W8);
not MGM_G11(MGM_W9,D);
and MGM_G12(MGM_W10,SE,MGM_W9);
and MGM_G13(MGM_W11,SETN,MGM_W10);
not MGM_G14(MGM_W12,SI);
and MGM_G15(ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W12,MGM_W11);
not MGM_G16(MGM_W13,D);
and MGM_G17(MGM_W14,SE,MGM_W13);
and MGM_G18(MGM_W15,SETN,MGM_W14);
and MGM_G19(ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W15);
not MGM_G20(MGM_W16,SE);
and MGM_G21(MGM_W17,MGM_W16,D);
and MGM_G22(MGM_W18,SETN,MGM_W17);
not MGM_G23(MGM_W19,SI);
and MGM_G24(ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W19,MGM_W18);
not MGM_G25(MGM_W20,SE);
and MGM_G26(MGM_W21,MGM_W20,D);
and MGM_G27(MGM_W22,SETN,MGM_W21);
and MGM_G28(ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI,SI,MGM_W22);
and MGM_G29(MGM_W23,SE,D);
and MGM_G30(MGM_W24,SETN,MGM_W23);
not MGM_G31(MGM_W25,SI);
and MGM_G32(ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI,MGM_W25,MGM_W24);
and MGM_G33(MGM_W26,SE,D);
and MGM_G34(MGM_W27,SETN,MGM_W26);
and MGM_G35(ENABLE_D_AND_SE_AND_SETN_AND_SI,SI,MGM_W27);
not MGM_G36(MGM_W28,SE);
and MGM_G37(MGM_W29,SETN,MGM_W28);
not MGM_G38(MGM_W30,SI);
and MGM_G39(ENABLE_NOT_SE_AND_SETN_AND_NOT_SI,MGM_W30,MGM_W29);
not MGM_G40(MGM_W31,SE);
and MGM_G41(MGM_W32,SETN,MGM_W31);
and MGM_G42(ENABLE_NOT_SE_AND_SETN_AND_SI,SI,MGM_W32);
not MGM_G43(MGM_W33,D);
and MGM_G44(MGM_W34,SETN,MGM_W33);
and MGM_G45(ENABLE_NOT_D_AND_SETN_AND_SI,SI,MGM_W34);
and MGM_G46(MGM_W35,SETN,D);
not MGM_G47(MGM_W36,SI);
and MGM_G48(ENABLE_D_AND_SETN_AND_NOT_SI,MGM_W36,MGM_W35);
not MGM_G49(MGM_W37,D);
not MGM_G50(MGM_W38,SE);
and MGM_G51(MGM_W39,MGM_W38,MGM_W37);
not MGM_G52(MGM_W40,SI);
and MGM_G53(ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W40,MGM_W39);
not MGM_G54(MGM_W41,D);
not MGM_G55(MGM_W42,SE);
and MGM_G56(MGM_W43,MGM_W42,MGM_W41);
and MGM_G57(ENABLE_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W43);
not MGM_G58(MGM_W44,D);
and MGM_G59(MGM_W45,SE,MGM_W44);
not MGM_G60(MGM_W46,SI);
and MGM_G61(ENABLE_NOT_D_AND_SE_AND_NOT_SI,MGM_W46,MGM_W45);
and MGM_G62(MGM_W47,SE,D);
not MGM_G63(MGM_W48,SI);
and MGM_G64(ENABLE_D_AND_SE_AND_NOT_SI,MGM_W48,MGM_W47);
not MGM_G65(MGM_W49,CLK);
not MGM_G66(MGM_W50,D);
and MGM_G67(MGM_W51,MGM_W50,MGM_W49);
not MGM_G68(MGM_W52,SE);
and MGM_G69(MGM_W53,MGM_W52,MGM_W51);
not MGM_G70(MGM_W54,SI);
and MGM_G71(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W54,MGM_W53);
not MGM_G72(MGM_W55,CLK);
not MGM_G73(MGM_W56,D);
and MGM_G74(MGM_W57,MGM_W56,MGM_W55);
not MGM_G75(MGM_W58,SE);
and MGM_G76(MGM_W59,MGM_W58,MGM_W57);
and MGM_G77(ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W59);
not MGM_G78(MGM_W60,CLK);
not MGM_G79(MGM_W61,D);
and MGM_G80(MGM_W62,MGM_W61,MGM_W60);
and MGM_G81(MGM_W63,SE,MGM_W62);
not MGM_G82(MGM_W64,SI);
and MGM_G83(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W64,MGM_W63);
not MGM_G84(MGM_W65,CLK);
not MGM_G85(MGM_W66,D);
and MGM_G86(MGM_W67,MGM_W66,MGM_W65);
and MGM_G87(MGM_W68,SE,MGM_W67);
and MGM_G88(ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W68);
not MGM_G89(MGM_W69,CLK);
and MGM_G90(MGM_W70,D,MGM_W69);
not MGM_G91(MGM_W71,SE);
and MGM_G92(MGM_W72,MGM_W71,MGM_W70);
not MGM_G93(MGM_W73,SI);
and MGM_G94(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W73,MGM_W72);
not MGM_G95(MGM_W74,CLK);
and MGM_G96(MGM_W75,D,MGM_W74);
not MGM_G97(MGM_W76,SE);
and MGM_G98(MGM_W77,MGM_W76,MGM_W75);
and MGM_G99(ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W77);
not MGM_G100(MGM_W78,CLK);
and MGM_G101(MGM_W79,D,MGM_W78);
and MGM_G102(MGM_W80,SE,MGM_W79);
not MGM_G103(MGM_W81,SI);
and MGM_G104(ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W81,MGM_W80);
not MGM_G105(MGM_W82,CLK);
and MGM_G106(MGM_W83,D,MGM_W82);
and MGM_G107(MGM_W84,SE,MGM_W83);
and MGM_G108(ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W84);
not MGM_G109(MGM_W85,D);
and MGM_G110(MGM_W86,MGM_W85,CLK);
not MGM_G111(MGM_W87,SE);
and MGM_G112(MGM_W88,MGM_W87,MGM_W86);
not MGM_G113(MGM_W89,SI);
and MGM_G114(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI,MGM_W89,MGM_W88);
not MGM_G115(MGM_W90,D);
and MGM_G116(MGM_W91,MGM_W90,CLK);
not MGM_G117(MGM_W92,SE);
and MGM_G118(MGM_W93,MGM_W92,MGM_W91);
and MGM_G119(ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI,SI,MGM_W93);
not MGM_G120(MGM_W94,D);
and MGM_G121(MGM_W95,MGM_W94,CLK);
and MGM_G122(MGM_W96,SE,MGM_W95);
not MGM_G123(MGM_W97,SI);
and MGM_G124(ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI,MGM_W97,MGM_W96);
not MGM_G125(MGM_W98,D);
and MGM_G126(MGM_W99,MGM_W98,CLK);
and MGM_G127(MGM_W100,SE,MGM_W99);
and MGM_G128(ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI,SI,MGM_W100);
and MGM_G129(MGM_W101,D,CLK);
not MGM_G130(MGM_W102,SE);
and MGM_G131(MGM_W103,MGM_W102,MGM_W101);
not MGM_G132(MGM_W104,SI);
and MGM_G133(ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI,MGM_W104,MGM_W103);
and MGM_G134(MGM_W105,D,CLK);
not MGM_G135(MGM_W106,SE);
and MGM_G136(MGM_W107,MGM_W106,MGM_W105);
and MGM_G137(ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI,SI,MGM_W107);
and MGM_G138(MGM_W108,D,CLK);
and MGM_G139(MGM_W109,SE,MGM_W108);
not MGM_G140(MGM_W110,SI);
and MGM_G141(ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI,MGM_W110,MGM_W109);
and MGM_G142(MGM_W111,D,CLK);
and MGM_G143(MGM_W112,SE,MGM_W111);
and MGM_G144(ENABLE_CLK_AND_D_AND_SE_AND_SI,SI,MGM_W112);
not MGM_G145(MGM_W113,D);
and MGM_G146(MGM_W114,SE,MGM_W113);
and MGM_G147(ENABLE_NOT_D_AND_SE_AND_SETN,SETN,MGM_W114);
and MGM_G148(MGM_W115,SE,D);
and MGM_G149(ENABLE_D_AND_SE_AND_SETN,SETN,MGM_W115);
// spec_gates_end
specify
// specify_block_begin
if(D===1'b0 && SI===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SE)) = (1.0,1.0);
if(SE===1'b0 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b0 && SI===1'b1 || D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(D===1'b1 && SE===1'b1)
// seq arc CLK --> Q
(posedge CLK => (Q : SI)) = (1.0,1.0);
ifnone
// seq arc CLK --> Q
(posedge CLK => (Q : D)) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b0 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b0 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b0 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b0)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
if(CLK===1'b1 && D===1'b1 && SE===1'b1 && SI===1'b1)
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
ifnone
// seq arc SETN --> Q
(SETN => Q) = (1.0,1.0);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
$width(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold D-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold D-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-HL CLK-LH
$setup(negedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup D-LH CLK-LH
$setup(posedge D &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_SE_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
negedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SETN_AND_SI === 1'b1),1.0,notifier);
// hold SE-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
negedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// hold SE-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-HL CLK-LH
$setup(negedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// setup SE-LH CLK-LH
$setup(posedge SE &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SETN_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// recovery SETN-LH CLK-LH
$recovery(posedge SETN &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
// removal SETN-LH CLK-LH
$removal(posedge SETN &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_NOT_SI === 1'b1),1.0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_NOT_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_NOT_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_NOT_SE_AND_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_NOT_SI === 1'b1)
,1.0,0,notifier);
$width(negedge SETN &&& (ENABLE_CLK_AND_D_AND_SE_AND_SI === 1'b1)
,1.0,0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-HL CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
negedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// hold SI-LH CLK-LH
$hold(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-HL CLK-LH
$setup(negedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// setup SI-LH CLK-LH
$setup(posedge SI &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),
posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN === 1'b1),1.0,notifier);
// mpw CLK_lh
$width(posedge CLK,1.0,0,notifier);
// mpw CLK_hl
$width(negedge CLK,1.0,0,notifier);
// mpw SETN_hl
$width(negedge SETN,1.0,0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_NOT_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_NOT_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_NOT_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK &&& (ENABLE_D_AND_SE_AND_SETN_AND_SI === 1'b1)
,1.0,notifier);
// period CLK
$period(posedge CLK,1.0,notifier);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module TIEH( Z );
output Z;
`ifdef FUNCTIONAL // functional //
TIEH_func TIEH_behav_inst(.Z(Z));
`else
TIEH_func TIEH_inst(.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module TIEL( ZN );
output ZN;
`ifdef FUNCTIONAL // functional //
TIEL_func TIEL_behav_inst(.ZN(ZN));
`else
TIEL_func TIEL_inst(.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XNOR2_X1( A2, A1, ZN );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
XNOR2_X1_func XNOR2_X1_behav_inst(.A2(A2),.A1(A1),.ZN(ZN));
`else
XNOR2_X1_func XNOR2_X1_inst(.A2(A2),.A1(A1),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
ifnone
// comb arc posedge A1 --> (ZN:A1)
(posedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (ZN:A1)
(negedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (ZN:A2)
(posedge A2 => (ZN:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (ZN:A2)
(negedge A2 => (ZN:A2)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XNOR2_X2( A2, A1, ZN );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
XNOR2_X2_func XNOR2_X2_behav_inst(.A2(A2),.A1(A1),.ZN(ZN));
`else
XNOR2_X2_func XNOR2_X2_inst(.A2(A2),.A1(A1),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
ifnone
// comb arc posedge A1 --> (ZN:A1)
(posedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (ZN:A1)
(negedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (ZN:A2)
(posedge A2 => (ZN:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (ZN:A2)
(negedge A2 => (ZN:A2)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XNOR2_X4( A2, A1, ZN );
input A1, A2;
output ZN;
`ifdef FUNCTIONAL // functional //
XNOR2_X4_func XNOR2_X4_behav_inst(.A2(A2),.A1(A1),.ZN(ZN));
`else
XNOR2_X4_func XNOR2_X4_inst(.A2(A2),.A1(A1),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
ifnone
// comb arc posedge A1 --> (ZN:A1)
(posedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (ZN:A1)
(negedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (ZN:A2)
(posedge A2 => (ZN:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (ZN:A2)
(negedge A2 => (ZN:A2)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XNOR3_X1( A2, A1, A3, ZN );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
XNOR3_X1_func XNOR3_X1_behav_inst(.A2(A2),.A1(A1),.A3(A3),.ZN(ZN));
`else
XNOR3_X1_func XNOR3_X1_inst(.A2(A2),.A1(A1),.A3(A3),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(A2===1'b0 && A3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A2===1'b1 && A3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A1 --> (ZN:A1)
(posedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (ZN:A1)
(negedge A1 => (ZN:A1)) = (1.0,1.0);
if(A2===1'b0 && A3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A2===1'b1 && A3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (ZN:A2)
(posedge A2 => (ZN:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (ZN:A2)
(negedge A2 => (ZN:A2)) = (1.0,1.0);
if(A1===1'b0 && A3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A3 --> (ZN:A3)
(posedge A3 => (ZN:A3)) = (1.0,1.0);
ifnone
// comb arc negedge A3 --> (ZN:A3)
(negedge A3 => (ZN:A3)) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XNOR3_X2( A2, A1, A3, ZN );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
XNOR3_X2_func XNOR3_X2_behav_inst(.A2(A2),.A1(A1),.A3(A3),.ZN(ZN));
`else
XNOR3_X2_func XNOR3_X2_inst(.A2(A2),.A1(A1),.A3(A3),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(A2===1'b0 && A3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A2===1'b1 && A3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A1 --> (ZN:A1)
(posedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (ZN:A1)
(negedge A1 => (ZN:A1)) = (1.0,1.0);
if(A2===1'b0 && A3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A2===1'b1 && A3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (ZN:A2)
(posedge A2 => (ZN:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (ZN:A2)
(negedge A2 => (ZN:A2)) = (1.0,1.0);
if(A1===1'b0 && A3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A3 --> (ZN:A3)
(posedge A3 => (ZN:A3)) = (1.0,1.0);
ifnone
// comb arc negedge A3 --> (ZN:A3)
(negedge A3 => (ZN:A3)) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XNOR3_X4( A2, A1, A3, ZN );
input A1, A2, A3;
output ZN;
`ifdef FUNCTIONAL // functional //
XNOR3_X4_func XNOR3_X4_behav_inst(.A2(A2),.A1(A1),.A3(A3),.ZN(ZN));
`else
XNOR3_X4_func XNOR3_X4_inst(.A2(A2),.A1(A1),.A3(A3),.ZN(ZN));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(A2===1'b0 && A3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A2===1'b1 && A3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A1 --> (ZN:A1)
(posedge A1 => (ZN:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (ZN:A1)
(negedge A1 => (ZN:A1)) = (1.0,1.0);
if(A2===1'b0 && A3===1'b1)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A2===1'b1 && A3===1'b0)
// comb arc A1 --> ZN
(A1 => ZN) = (1.0,1.0);
if(A1===1'b0 && A3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (ZN:A2)
(posedge A2 => (ZN:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (ZN:A2)
(negedge A2 => (ZN:A2)) = (1.0,1.0);
if(A1===1'b0 && A3===1'b1)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b1 && A3===1'b0)
// comb arc A2 --> ZN
(A2 => ZN) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
ifnone
// comb arc posedge A3 --> (ZN:A3)
(posedge A3 => (ZN:A3)) = (1.0,1.0);
ifnone
// comb arc negedge A3 --> (ZN:A3)
(negedge A3 => (ZN:A3)) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc A3 --> ZN
(A3 => ZN) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XOR2_X1( A2, A1, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
XOR2_X1_func XOR2_X1_behav_inst(.A2(A2),.A1(A1),.Z(Z));
`else
XOR2_X1_func XOR2_X1_inst(.A2(A2),.A1(A1),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
ifnone
// comb arc posedge A1 --> (Z:A1)
(posedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (Z:A1)
(negedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (Z:A2)
(posedge A2 => (Z:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (Z:A2)
(negedge A2 => (Z:A2)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XOR2_X2( A2, A1, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
XOR2_X2_func XOR2_X2_behav_inst(.A2(A2),.A1(A1),.Z(Z));
`else
XOR2_X2_func XOR2_X2_inst(.A2(A2),.A1(A1),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
ifnone
// comb arc posedge A1 --> (Z:A1)
(posedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (Z:A1)
(negedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (Z:A2)
(posedge A2 => (Z:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (Z:A2)
(negedge A2 => (Z:A2)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XOR2_X4( A2, A1, Z );
input A1, A2;
output Z;
`ifdef FUNCTIONAL // functional //
XOR2_X4_func XOR2_X4_behav_inst(.A2(A2),.A1(A1),.Z(Z));
`else
XOR2_X4_func XOR2_X4_inst(.A2(A2),.A1(A1),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
ifnone
// comb arc posedge A1 --> (Z:A1)
(posedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (Z:A1)
(negedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (Z:A2)
(posedge A2 => (Z:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (Z:A2)
(negedge A2 => (Z:A2)) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XOR3_X1( A2, A1, A3, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
XOR3_X1_func XOR3_X1_behav_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));
`else
XOR3_X1_func XOR3_X1_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(A2===1'b0 && A3===1'b1)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A2===1'b1 && A3===1'b0)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A1 --> (Z:A1)
(posedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (Z:A1)
(negedge A1 => (Z:A1)) = (1.0,1.0);
if(A2===1'b0 && A3===1'b0)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A2===1'b1 && A3===1'b1)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A1===1'b0 && A3===1'b1)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b1 && A3===1'b0)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (Z:A2)
(posedge A2 => (Z:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (Z:A2)
(negedge A2 => (Z:A2)) = (1.0,1.0);
if(A1===1'b0 && A3===1'b0)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b1 && A3===1'b1)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A3 --> (Z:A3)
(posedge A3 => (Z:A3)) = (1.0,1.0);
ifnone
// comb arc negedge A3 --> (Z:A3)
(negedge A3 => (Z:A3)) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XOR3_X2( A2, A1, A3, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
XOR3_X2_func XOR3_X2_behav_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));
`else
XOR3_X2_func XOR3_X2_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(A2===1'b0 && A3===1'b1)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A2===1'b1 && A3===1'b0)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A1 --> (Z:A1)
(posedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (Z:A1)
(negedge A1 => (Z:A1)) = (1.0,1.0);
if(A2===1'b0 && A3===1'b0)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A2===1'b1 && A3===1'b1)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A1===1'b0 && A3===1'b1)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b1 && A3===1'b0)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (Z:A2)
(posedge A2 => (Z:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (Z:A2)
(negedge A2 => (Z:A2)) = (1.0,1.0);
if(A1===1'b0 && A3===1'b0)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b1 && A3===1'b1)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A3 --> (Z:A3)
(posedge A3 => (Z:A3)) = (1.0,1.0);
ifnone
// comb arc negedge A3 --> (Z:A3)
(negedge A3 => (Z:A3)) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine
`celldefine
module XOR3_X4( A2, A1, A3, Z );
input A1, A2, A3;
output Z;
`ifdef FUNCTIONAL // functional //
XOR3_X4_func XOR3_X4_behav_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));
`else
XOR3_X4_func XOR3_X4_inst(.A2(A2),.A1(A1),.A3(A3),.Z(Z));
// spec_gates_begin
// spec_gates_end
specify
// specify_block_begin
if(A2===1'b0 && A3===1'b1)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A2===1'b1 && A3===1'b0)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A1 --> (Z:A1)
(posedge A1 => (Z:A1)) = (1.0,1.0);
ifnone
// comb arc negedge A1 --> (Z:A1)
(negedge A1 => (Z:A1)) = (1.0,1.0);
if(A2===1'b0 && A3===1'b0)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A2===1'b1 && A3===1'b1)
// comb arc A1 --> Z
(A1 => Z) = (1.0,1.0);
if(A1===1'b0 && A3===1'b1)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b1 && A3===1'b0)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A2 --> (Z:A2)
(posedge A2 => (Z:A2)) = (1.0,1.0);
ifnone
// comb arc negedge A2 --> (Z:A2)
(negedge A2 => (Z:A2)) = (1.0,1.0);
if(A1===1'b0 && A3===1'b0)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b1 && A3===1'b1)
// comb arc A2 --> Z
(A2 => Z) = (1.0,1.0);
if(A1===1'b0 && A2===1'b1)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
if(A1===1'b1 && A2===1'b0)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
ifnone
// comb arc posedge A3 --> (Z:A3)
(posedge A3 => (Z:A3)) = (1.0,1.0);
ifnone
// comb arc negedge A3 --> (Z:A3)
(negedge A3 => (Z:A3)) = (1.0,1.0);
if(A1===1'b0 && A2===1'b0)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
if(A1===1'b1 && A2===1'b1)
// comb arc A3 --> Z
(A3 => Z) = (1.0,1.0);
// specify_block_end
endspecify
`endif
endmodule
`endcelldefine