| 14.3.4 other better layout practices (guidelines) for latch-up prevention |
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| High voltage circuits are highly sensitive for latch-up and hence attention shall be paid for how various high voltage devices are placed adjacent to each other. As much spacing and guard rings shall be put as possible depending upon space availability within that part of the circuit layout. Some of the guidelines to increase latch-up immunity are as below. |
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| 1. Place HVNMOS and HVPMOS as far apart as possible with double guard ring. |
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| 2. Place double guard ring (substrate tap connected to VSS and Nwell connected to VDD) between High Voltage and low voltage (or medium voltage) devices. |
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| 3. Use butted source and substrate contacts as much as possible. If because of required body bias reason they cannot be butted then keep minimum distance between source active region and the substrate-tap active regions. |
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| 4. Maximize the number of contacts and metal width in all guard rings. |
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| 5. Widen the widths of guard rings if found emptier space after the complete block layout. |
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