| RULE NO.,DESCRIPTION,LAYOUT RULE |
| MIM.1,"Minimum MiM bottom plate (1) spacing to the bottom plate metal |
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| (whether adjacent MiM or routing metal)",1.2 |
| MIM.2,"Minimum MiM bottom plate (1) overlap of Via2 layer |
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| [This is applicable for via2 within 1.06um oversize of FuseTop |
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| layer (referenced to virtual bottom plate)]",0.4 |
| MIM.3,Minimum MiM bottom plate overlap of Top plate,0.6 |
| MIM.4,Minimum MiM top plate (FuseTop) overlap of Via2,0.4 |
| MIM.5,"Minimum spacing between top plate and the Via2 connecting to the |
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| bottom plate",0.4 |
| MIM.6,Minimum spacing between unrelated top plates,0.6 |
| MIM.7,Min FuseTop enclosure by CAP_MK,0 |
| MIM.8a,Minimum MIM cap area (defined by FuseTop area),5*5 um2 |
| MIM.8b,"Maximum single MIM Cap area (Use multiple MIM caps in |
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| parallel connection if bigger capacitors are required)",100*100 um2 |
| MIM.9,Min. via spacing for sea of via on MIM top plate,0.5 |
| MIM.10,"(a) There cannot be any Via1 touching MIM bottom plate Metal2 |
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| (b) MIM bottom plate Metal2 can only be connected through the higher Via (Via2).", |
| MIM.11,"Bottom plate of multiple MIM caps can be shared (for common |
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| nodes) as long as total MIM area with that single common plate |
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| does not exceed “MIM.8b” rule.", |
| MIM.12*,"For MIM need to identify its' length and width, use MIM_L_MK to |
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| mark MIM capacitor's length", |
| Guideline,There cannot be any sensitive matching analog circuitry underneath MIM., |
