| 9.4 Mismatch MOSFET Modeling Results |
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| 9.4.1 3.3V NMOS and PMOS mismatch verification plots |
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| Biasing Conditions (positive sign for NMOS, negative for PMOS): |
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| - Vtlin=Vg@ Vds= 0.1V; Vt @ Id= 0.1μA*(W/L) |
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| - Idsat=Id @Vg=3.3V, Vd= 3.3V, where Vbulk = 0V |
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| .. image:: images/5_Mismatch1.png |
| :width: 600 |
| :align: center |
| :alt: 3.3V NMOS and PMOS mismatch verification plots |
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| 9.4.2 6V NMOS and PMOS mismatch verification plots |
| ................................................... |
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| Biasing Conditions (positive sign for NMOS, negative for PMOS): |
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| - Vtlin@ Vds= 0.1V; Vt @ Id= 0.1μA*(W/L) |
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| - Idsat @Vg=6V, Vd= 6V, where Vbulk = 0V |
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| .. image:: images/5_Mismatch2.png |
| :width: 600 |
| :align: center |
| :alt: 6V NMOS and PMOS mismatch verification plots |
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