Sign in
foss-eda-tools
/
gf180mcu-pdk
/
7886e3ca94fae1c79691e45b1d0d4dcdc5ba681f
/
.
/
docs
/
physical_verification
/
design_manual
/
drm_01.rst
blob: bd24cac7eb87ee2cde119ba955951a5a5d3beadb [
file
] [
log
] [
blame
]
1.0
Purpose
===========
This
document provides topological layout rules to generate masks
in
a
0.18
μ
m
3.3V
/(
5V
)
6V
dual
-
gate MCU
Technology
Processes
.
