| Signal,Direction,Description |
| CLK,Input,"Clock for the memory. Rising edge triggers |
| |
| operation. All inputs are latched at rising edge of the |
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| clock signal" |
| CEN,Input,"Memory Enable, Active Low. When CEN is Low, the |
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| memory is enabled. When CEN input is High, the |
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| memory is deactivated but internal states are |
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| retained. CEN must be high before 1st running cycle." |
| A[6:0],Input,"Address Input. This Address input port is used to |
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| address the location to be written during the write |
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| cycle and read during the read cycle." |
| GWEN,Input,"Write Enable Input. The RAM is in write cycle when |
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| GWEN is low. The RAM is in read cycle when |
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| GWEN is high." |
| WEN[7:0],Input,"Bit Write Mask, Active Low. When the memory is in |
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| the write cycle, selectively write into individual |
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| outputs are controlled by WEN[7:0]. For example, if |
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| CEN, GWEN, WEN[0] are low and WEN[7:1] are |
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| high, only D[0] will write into the addressed location and |
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| D[7:1] will be ignored during CLK low to high transition." |
| D[7:0],Input,"Data input bus. The data input bus is used to write |
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| data into the memory location specified by address |
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| input port during the write cycle." |
| Q[7:0],output,"Data output bus. It outputs the contents of the |
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| memory location addressed by the Address Input signals." |
| VDD,Power,Power pin. |
| VSS,Ground,Ground pin. |
