| RULE NO.,DESCRIPTION,LV,MV,Comment |
| ,FOR LV and MV,,, |
| IO.3,"a1\) PCOMP in Nwell directly connected to I/O pad must be |
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| surrounded by Nwell tap inside the Nwell (Exclude the case when |
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| each PMOS transistor have full width butting to well tap).",,, |
| ,"a2\) It should also be directly surrounded by PCOMP guard ring |
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| outside Nwell. PCOMP guard ring shall be connected to the lowest |
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| potential. Max space of guard ring PCOMP to the PCOMP in |
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| Nwell directly connected to the I/O pad. |
| ",15,15,Rule |
| ,"b\) Within 10um from the edge of the PCOMP connected to I/O |
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| Pad (marked by Latchup_MK): Max P substrate tap distance to |
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| NCOMP outside Nwell (irrespective of its direct connection to Pad)",5,5,Rule |
| IO.4,"Minimum recommended PCOMP guard ring width: |
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| (Maximize contact to guard uniformly. As a guideline, ratio of |
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| total contact area to the active area of the guard ring should be |
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| more than 5%). |
| ",2,2,Rule |
