| RULE NO.,DESCRIPTION,LV,MV,Comment |
| IO.0,"To flag I/O latch-up related violation: |
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| i. Non well tap COMP directly connected to PAD is |
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| recommended to be marked by “Latchup_MK” layer.",-,-,Guidelines |
| ,"(b) Min/max Latchup_MK layer overlap of COMP (directly |
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| connected to Pad)",0,0,Guidelines |
| ,FOR LV and MV,,, |
| IO.1,"(a1) NCOMP in PSub directly connected to I/O pad must be |
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| surrounded by Psub tap inside the Psub without any PCOMP in |
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| NWELL in between (Exclude the case when each NMOS |
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| transistor have full width butting to well tap).",,, |
| ,"(a2) It should also be directly surrounded by an Nwell guard ring |
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| (Non broken NCOMP ring inside Nwelll). Nwell guard ring shall |
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| be connected to the most positive supply. Max space of Nwell |
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| guard ring to the NCOMP in Psub directly connected to I/O pad.",15,15,Rule |
| ,"(b) Within 15um from the edge of the NCOMP connected to I/O |
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| pad (marked by Latchup_MK): Max Nwell tap distance to |
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| PCOMP inside Nwell (irrespective of its direct connection to Pad)",2,2,Rule |
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| IO.2,"Minimum recommended Nwell guard ring width: |
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| (Maximize contact to guard uniformly. As a guideline, ratio of |
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| total contact area to the active area of the guard ring should be |
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| more than 5%).",2,2,Rule |
