| RULE NO.,DESCRIPTION,LAYOUT RULE |
| MIMTM.1,Minimum MiM bottom plate (1) spacing to the bottom plate metal (whether adjacent MiM or routing metal),1.2 |
| MIMTM.2,Minimum MiM bottom plate (1) overlap of “Vian-1” layer [This is applicable for “Vian-1” within 1.06um oversize of FuseTop layer (referenced to virtual bottom plate)],0.4 |
| MIMTM.3,Minimum MiM bottom plate overlap of Top plate,0.6 |
| MIMTM.4,Minimum MiM top plate (FuseTop) overlap of “Vian-1”,0.4 |
| MIMTM.5,Minimum spacing between top plate and the “Vian-1” connecting to the bottom Plate,0.4 |
| MIMTM.6,Minimum spacing between unrelated top plates,0.6 |
| MIMTM.7,Min FuseTop enclosure by CAP_MK,0 |
| MIMTM.8a,Minimum MIM cap area (defined by FuseTop area),5*5um2 |
| MIMTM.8b,Maximum single MIM Cap area (Use multiple MIM caps in parallel connection if bigger capacitors are required),100*100um2 |
| MIMTM.9,Min. Via (“Vian-1”) spacing for sea of Via on MIM top plate,0.5 |
| MIMTM.10,"(a) There cannot be any “Vian-2” touching MIM bottom plate “Metaln-1” |
| (b) MIM bottom plate “Metaln-1” can only be connected through the higher Via (“Vian-1”).", |
| MIMTM.11,Bottom plate of multiple MIM caps can be shared (for common nodes) as long as total MIM area with that single common plate does not exceed “MIMTM.8b” rule., |
| MIMTM.12*,"For MIM need to identify its' length and width, use MIM_L_MK to mark MIM capacitor's length", |
| Guideline,There cannot be any sensitive matching analog circuitry underneath MIM., |
