Sign in
foss-eda-tools
/
gf180mcu-pdk
/
2042daf3a53263be9bac37ab9b172eff928420e9
/
.
/
docs
/
physical_verification
/
design_manual
/
tables_clear
/
38_DRC_BJT_103.csv
blob: 84f87d3fd276f9101f8c15e1c974d16e182b4bf1 [
file
] [
log
] [
blame
]
RULE NO
.,
DESCRIPTION
,
LAYOUT RULE
Layer
,
DRC_BJT
---
Marking
for
Vertical
NPN
and
PNP BJT
,
BJT
.
1
,
Min
.
DRC_BJT overlap of DNWELL
for
NPN BJT
,
0
BJT
.
2
,
Min
.
DRC_BJT overlap of PCOM
in
Psub
,
0
BJT
.
3
,
Minimum
space of DRC_BJT layer to unrelated COMP
,
0.1