| verilog2def -verilog /home/ahmedg/openlane_dev/designs/spm/runs/abs_fp/results/synthesis/spm.synthesis.v -lef /home/ahmedg/openlane_dev/designs/spm/runs/abs_fp/tmp//merged.lef -liberty /home/ahmedg/openlane_dev/designs/spm/runs/abs_fp/tmp//trimmed.lib -top_module spm -site unitehd -tracks /home/ahmedg/openlane_dev/pdks//ef-skywater-s8/EFS8A//libs.tech/openlane/common_tracks.info -units 1000 -utilization 50 -aspect_ratio 1 -core_space 3.36 -def /home/ahmedg/openlane_dev/designs/spm/runs/abs_fp/tmp/floorplan/verilog2def_broken.def -verbose | |