| proc run_yosys {args} { |
| set ::env(CURRENT_STAGE) synthesis |
| TIMER::timer_start |
| try_catch yosys \ |
| -c $::env(SYNTH_SCRIPT) \ |
| -l $::env(yosys_log_file_tag).log \ |
| |& tee $::env(TERMINAL_OUTPUT) |
| |
| try_catch sta $::env(SCRIPTS_DIR)/sta.tcl \ |
| |& tee $::env(TERMINAL_OUTPUT) $::env(opensta_log_file_tag).log |
| |
| TIMER::timer_stop |
| exec echo "[TIMER::get_runtime]" >> $::env(yosys_log_file_tag)_runtime.txt |
| } |
| |
| proc run_synthesis {args} { |
| # in-place insertion |
| run_yosys |
| if {$::env(RUN_SIMPLE_CTS)} { |
| simple_cts \ |
| -verilog $::env(yosys_result_file_tag).v \ |
| -fanout $::env(CLOCK_BUFFER_FANOUT) \ |
| -clk_net $::env(CLOCK_NET) \ |
| -root_clk_buf $::env(ROOT_CLK_BUFFER) \ |
| -clk_buf $::env(CLK_BUFFER) \ |
| -clk_buf_input $::env(CLK_BUFFER_INPUT) \ |
| -clk_buf_output $::env(CLK_BUFFER_OUTPUT) \ |
| -output $::env(yosys_result_file_tag).v |
| } |
| } |
| |
| proc verilog_elaborate {args} { |
| set synth_script_old $::env(SYNTH_SCRIPT) |
| set ::env(SYNTH_SCRIPT) $::env(SCRIPTS_DIR)/synth_top.tcl |
| run_yosys |
| set ::env(SYNTH_SCRIPT) $synth_script_old |
| } |
| |
| package provide openlane 0.9 |
