scripts/tcl_commands/cts.tcl

# Copyright (c) Efabless Corporation. All rights reserved.
# See LICENSE file in the project root for full license information.
global script_path
set script_path [ file dirname [ file normalize [ info script ] ] ]
source $script_path/../utils/utils.tcl

proc set_core_dims {args} {
	set options {{-log_path required}}
	parse_key_args "set_core_dims" args values $options
	set log_path $values(-log_path)
	set FpOutDef $::env(ioPlacer_tmp_file_tag).def
	set def_units $::env(DEF_UNITS_PER_MICRON)
	set coreinfo [join [exec $::env(SCRIPTS_DIR)/extract_coreinfo.sh $FpOutDef] " "]
	set sites_per_row [lindex $coreinfo 8]
	set step [lindex $coreinfo 9]
	set core_area_llx [expr { [lindex $coreinfo 4]/double($def_units) }]
	set core_area_urx [expr { ([lindex $coreinfo 6]+$step*$sites_per_row)/double($def_units) }]
	set core_area_lly [expr { [lindex $coreinfo 5]/double($def_units) }]
	set core_area_ury [expr { [lindex $coreinfo 7]/double($def_units) }]
	set ::env(CORE_WIDTH) [expr {$core_area_urx - $core_area_llx} ]
	set ::env(CORE_HEIGHT) [expr {$core_area_ury - $core_area_lly} ]
	puts "$::env(CORE_WIDTH) $::env(CORE_HEIGHT)"
}

proc gen_cts_config {args} {
	set options {{-verilog required} {-def required} \
			{-root_buffer required} 
			{-output required} 
			{-toler required} {-target_skew required}}
	parse_key_args "gen_cts_config" args values $options
	set ::env(CTS_VERILOG_INPUT) $values(-verilog)
	set ::env(CTS_DEF_INPUT) $values(-def)
	set ::env(CTS_ROOT_BUFFER) $values(-root_buffer)
	# check
	set ::env(CTS_PERCENTILE) 0.075 
	set ::env(CTS_TARGET_SKEW) $values(-target_skew)
	set ::env(CTS_TOLER) $values(-toler)
	exec envsubst < ./scripts/cts/cts.config > $values(-output)
}

proc gen_clock_tree {args} {
	set options {{-config required}}
	parse_key_args "gen_clock_tree" args values $options
	set cts_config $values(-config)

	exec ./scripts/cts/runTritonCTS_mod.tcl \
		-configFilePath=$cts_config \
		-scriptsPath=$::env(OPENROAD)/TritonCTS/scripts \
		-techFilesPath=$::env(CTS_TECH_DIR) \
		-lefDefParserPath=$::env(OPENROAD)/TritonCTS/bin/lefdef2cts \
		-executablePath=$::env(OPENROAD)/TritonCTS/bin/genHtree \
		-legalizerPath=$::env(OPENROAD)/bin/opendp \
		-outputPath=$::env(RESULTS_DIR)/cts |& tee $::env(TERMINAL_OUTPUT) $::env(cts_log_file_tag).log

        exec mv $::env(RESULTS_DIR)/cts/final.v $::env(cts_result_file_tag).v
        exec mv $::env(RESULTS_DIR)/cts/cts_final.def $::env(cts_result_file_tag).def
}

proc simple_cts {args} {
	set options {
		{-verilog required}
		{-fanout required}
		{-clk_net required}
		{-root_clk_buf required}
		{-clk_buf required}
		{-clk_buf_input required}
		{-clk_buf_output required}
		{-output required}
	}
	parse_key_args "simple_cts" args values $options
	global script_path
	set tmp $::env(yosys_tmp_file_tag).v
	file copy $values(-verilog) $tmp
	set script $script_path/../cts/cts_simple.pl
	try_catch $script \
		$tmp \
		$values(-fanout) \
		$values(-clk_net) \
		$values(-root_clk_buf) \
		$values(-clk_buf) \
		$values(-clk_buf_input) \
		$values(-clk_buf_output) \
		|& tee $values(-output)
}

package provide openlane 0.9