| set ::env(DESIGN_NAME) "zipdiv" | |
| set ::env(VERILOG_FILES) "./designs/zipdiv/src/zipdiv.v" | |
| set ::env(SDC_FILE) "./designs/zipdiv/src/zipdiv.sdc" | |
| set ::env(CLOCK_PERIOD) "2.5" | |
| set ::env(CLOCK_PORT) "i_clk" | |
| set ::env(FP_CORE_MARGIN) 3.36 | |
| set ::env(GLB_RT_ADJUSTMENT) 0.15 | |
| set ::env(SYNTH_STRATEGY) 2 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) |