| set ::env(DESIGN_NAME) "wb_conbus_top" | |
| set ::env(VERILOG_FILES) [glob ./designs/wb_conbus_top/src/*.v] | |
| set ::env(CLOCK_PERIOD) "10.000" | |
| set ::env(CLOCK_PORT) "clk_i" | |
| set ::env(FP_CORE_UTIL) 5 | |
| set ::env(SYNTH_STRATEGY) 2 | |
| set ::env(PL_TARGET_DENSITY) 0.5 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) |