blob: 46e2d8996b4057b2e54f96dd53edfb56e6beb777 [file] [log] [blame] [edit]
package require openlane
prep -design striVe_toplevel -tag toplevel -overwrite
#config
set padframe_cfg $::env(DESIGN_DIR)/src/padframe.cfg
set padframe_def $::env(DESIGN_DIR)/src/def/padframe.def
set core_def $::env(DESIGN_DIR)/src/def/core.def
set lefs [glob $::env(DESIGN_DIR)/src/lef/*.lef]
set area [padframe_extract_area -cfg $padframe_cfg]
set ::env(DIE_AREA) $area
set ::env(CORE_AREA) $area
set ::env(FP_SIZING) absolute
add_lefs -src $lefs
verilog_elaborate
# verilog2def for nets
chip_floorplan
merge_components -input1 $padframe_def -input2 $core_def -output $::env(CURRENT_DEF)
run_routing
# run_magic