| # User config | |
| set ::env(DESIGN_NAME) striVe_ChipCore | |
| # Change if needed | |
| set ::env(VERILOG_FILES) [glob "./designs/striVe_flat/src/*/*.v" ] | |
| # Fill this | |
| set ::env(CLOCK_PERIOD) "50" | |
| set ::env(CLOCK_PORT) "xclk" | |
| set ::env(RUN_SIMPLE_CTS) 0 | |
| set ::env(FILL_INSERTION) 1 | |
| set ::env(GLB_RT_LI1_ADJUSTMENT) 0.75 | |
| set ::env(GLB_RT_MET1_ADJUSTMENT) 0.75 | |
| set ::env(FP_CORE_MARGIN) 160 | |
| set ::env(CLOCK_NET) "clk" |