designs/des/config.tcl

set ::env(DESIGN_NAME) "des"

set ::env(VERILOG_FILES) [glob ./designs/des/src/*.v]

set ::env(CLOCK_PERIOD) "2.000"
set ::env(CLOCK_PORT) "clk"

set ::env(FP_CORE_MARGIN) 3.36
set ::env(GLB_RT_ADJUSTMENT) 0.1
set ::env(SYNTH_STRATEGY) 2