| proc init_design {design_name config_tag} { |
| set src "./designs/$design_name/src" |
| set config_path "./designs/${design_name}/$config_tag.tcl" |
| set base_config_path "./designs/${design_name}/base_config.tcl" |
| exec mkdir -p "./designs/$design_name" |
| exec touch $config_path |
| |
| puts "Populating $config_path.." |
| |
| set config_user \ |
| " |
| # User config |
| set ::env(DESIGN_NAME) ${design_name} |
| |
| # Change if needed |
| set ::env(VERILOG_FILES) \[glob $src/*.v\] |
| |
| # Fill this |
| set ::env(CLOCK_PERIOD) \"100000\" |
| set ::env(CLOCK_PORT) \"my_design_clock\" |
| " |
| set config_file [open $config_path w] |
| puts $config_file $config_user |
| #puts $config_file $config_default |
| close $config_file |
| puts "Finished populating:\n$config_path \nPlease modify CLOCK_PORT, CLOCK_PERIOD and add your advanced settings to $config_path" |
| } |