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foss-eda-tools
/
efabless
/
openlane
/
refs/heads/old/develop_macro
/
.
/
designs
/
zipdiv
/
base_config.tcl
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set
::
env(DESIGN_NAME)
"zipdiv"
set
::
env(VERILOG_FILES)
"./designs/zipdiv/src/zipdiv.v"
set
::
env(SDC_FILE)
"./designs/zipdiv/src/zipdiv.sdc"
set
::
env(CLOCK_PERIOD)
"2.5"
set
::
env(CLOCK_PORT)
"i_clk"
