Sign in
foss-eda-tools
/
efabless
/
openlane
/
refs/heads/old/develop_macro
/
.
/
designs
/
sub86
/
base_config.tcl
blob: 6fcb7eb312fd0922d36cf97930f373e4df71a2e9 [
file
] [
log
] [
blame
] [
edit
]
set
::
env(DESIGN_NAME)
"sub86"
set
::
env(VERILOG_FILES)
"./designs/sub86/src/sub86.v"
set
::
env(SDC_FILE)
"./designs/sub86/src/sub86.sdc"
set
::
env(CLOCK_PERIOD)
"5.000"
set
::
env(CLOCK_PORT)
"CLK"
