designs/oram/src/design.v

module oram(clk, rst, dout);
    input clk, rst;
    output reg [15:0] dout;
    reg [7:0] cnt;
    wire web;
    wire [15:0] dout_w;

    sram_16_256_8_scn4m_subm sram (.clk0(clk), .csb0(1'b0), .web0(web), .wmask0(2'b11), .addr0(8'd0), .din0({8'd0, cnt}), .dout0(dout_w));
    always @ (posedge clk or posedge rst) begin
      if (rst) begin
        cnt <= 8'd0;
        dout <= 16'd0;
      end
      else begin
        cnt <= cnt + 1'b1;
        dout <= ~web? dout_w : dout;
      end
    end

    assign web = ~cnt[0];
endmodule

/* module sram_16_256_8_scn4m_subm( */
/* // Port 0: RW */
/*     clk0,csb0,web0,wmask0,addr0,din0,dout0 */
/*   ); */

/*   parameter NUM_WMASKS = 2 ; */
/*   parameter DATA_WIDTH = 16 ; */
/*   parameter ADDR_WIDTH = 8 ; */
/*   parameter RAM_DEPTH = 1 << ADDR_WIDTH; */
/*   // FIXME: This delay is arbitrary. */
/*   parameter DELAY = 3 ; */

/*   input  clk0; // clock */
/*   input   csb0; // active low chip select */
/*   input  web0; // active low write control */
/*   input [NUM_WMASKS-1:0]   wmask0; // write mask */
/*   input [ADDR_WIDTH-1:0]  addr0; */
/*   input [DATA_WIDTH-1:0]  din0; */
/*   output [DATA_WIDTH-1:0] dout0; */

/* endmodule */