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foss-eda-tools
/
efabless
/
openlane
/
refs/heads/old/develop_macro
/
.
/
designs
/
cpu6502
/
base_config.tcl
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set
::
env(DESIGN_NAME)
"cpu6502"
set
::
env(VERILOG_FILES)
"./designs/cpu6502/src/cpu6502.v"
set
::
env(SDC_FILE)
"./designs/cpu6502/src/cpu6502.sdc"
set
::
env(CLOCK_PERIOD)
"10.000"
set
::
env(CLOCK_PORT)
"clk"
