| set ::env(DESIGN_NAME) "aes" | |
| set ::env(VERILOG_FILES) "./designs/aes/src/aes.v" | |
| set ::env(SDC_FILE) "./designs/aes/src/aes.sdc" | |
| set ::env(CLOCK_PERIOD) "5.000" | |
| set ::env(CLOCK_PORT) "clk" | |
| set ::env(FP_CORE_MARGIN) 3.36 | |
| set ::env(GLB_RT_ADJUSTMENT) 0.15 | |
| set ::env(SYNTH_STRATEGY) 2 |