scripts/openroad/or_diodes.tcl

set input_def $::env(CURRENT_DEF)
set input_lef $::env(MERGED_LEF_UNPADDED)
set output_def $::env(SAVE_DEF)
set antenna_cell scs8hd_diode_2
set antenna_pin DIODE

proc add_antenna_cell { net antenna_cell_name sink_inst antenna_inst_name antenna_pin} {
	set block [[[::ord::get_db] getChip] getBlock]
	set net_name [$net getName]
	set antenna_master [[::ord::get_db] findMaster $antenna_cell_name]
	set antenna_mterm [$antenna_master getMTerms]

	set inst_loc [$sink_inst getLocation]
	set inst_loc_x [lindex [$sink_inst getLocation] 0]
	set inst_loc_y [lindex [$sink_inst getLocation] 1]
	set inst_ori [$sink_inst getOrient]

	#create ant cell
	set antenna_inst [odb::dbInst_create $block $antenna_master $antenna_inst_name]
	set antenna_iterm [$antenna_inst findITerm $antenna_pin]

	$antenna_inst setLocation $inst_loc_x $inst_loc_y
	$antenna_inst setOrient $inst_ori
	$antenna_inst setPlacementStatus PLACED
	odb::dbITerm_connect $antenna_iterm $net

}

proc get_nets {} {
	set block [[[::ord::get_db] getChip] getBlock]
	set nets [$block getNets]
	return $nets
}

read_lef $input_lef
read_def $input_def
set nets [get_nets]
set index 0
foreach net $nets {
	set net_name [$net getName]
	set iterms [$net getITerms]
	foreach iterm $iterms {
		set net_inst [$iterm getInst]
		set inst_name ANTENNA_$index
		set net_inst_name [$net_inst getName]
		puts "Adding $inst_name of $net_name cell $net_inst_name "	
		add_antenna_cell $net $antenna_cell $net_inst $inst_name $antenna_pin
		set index [expr $index + 1]
	}
}
legalize_placement
#detailed_placement
write_def $::env(SAVE_DEF)
write_verilog $::env(yosys_result_file_tag)_diodes.v