scripts/base.sdc

create_clock [get_ports $::env(CLOCK_PORT)]  -name $::env(CLOCK_PORT)  -period $::env(CLOCK_PERIOD)
set IO_PCT  0.2
set input_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]
puts "Setting output delay to: $output_delay_value"
puts "Setting input delay to: $input_delay_value"


create_clock -name vclk -period 12.0 $::env(CLOCK_PORT)
set input_delay_value  [expr $::env(CLOCK_PERIOD) * $IO_PCT]
set output_delay_value [expr $::env(CLOCK_PERIOD) * $IO_PCT]

set clk_indx [lsearch [all_inputs] [get_port $::env(CLOCK_PORT)]]
set rst_indx [lsearch [all_inputs] [get_port resetn]]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx]
set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]


# correct resetn
set_input_delay $input_delay_value  -clock [get_clocks vclk] $all_inputs_wo_clk_rst
set_input_delay 0.0 -clock [get_clocks vclk] {resetn}
set_output_delay $output_delay_value  -clock [get_clocks vclk] [all_outputs]

# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.]
puts "Setting load to: $cap_load"
set_load  $cap_load [all_outputs]