| set ::env(DESIGN_NAME) "usb" | |
| set ::env(VERILOG_FILES) "./designs/usb/src/usb2p0_core.v" | |
| set ::env(CLOCK_PERIOD) "15.000" | |
| set ::env(CLOCK_PORT) "clk_48" | |
| set ::env(PL_TARGET_DENSITY) 0.5 | |
| set ::env(FP_CORE_UTIL) 50 | |
| set ::env(SYNTH_STRATEGY) 2 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) |