| set ::env(DESIGN_NAME) "sub86" | |
| set ::env(VERILOG_FILES) "./designs/sub86/src/sub86.v" | |
| set ::env(SDC_FILE) "./designs/sub86/src/sub86.sdc" | |
| set ::env(CLOCK_PERIOD) "5.000" | |
| set ::env(CLOCK_PORT) "CLK" | |
| set ::env(FP_CORE_MARGIN) 3.36 | |
| set ::env(GLB_RT_ADJUSTMENT) 0.15 | |
| set ::env(SYNTH_STRATEGY) 2 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) | |
| set ::env(FP_CORE_UTIL) 40 | |
| set ::env(PL_TARGET_DENSITY) 0.4 |