designs/striVe_levelshift/config.tcl

# User config
set ::env(DESIGN_NAME) striVe_levelshift

# Change if needed
set ::env(VERILOG_FILES) ./designs/striVe_levelshift/src/striVe_levelshift.v

# Fill this
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "SCK"


set ::env(CLOCK_NET) $::env(CLOCK_PORT)
set ::env(PDN_CFG) ./designs/striVe_levelshift/pdn.tcl
#set ::env(FP_CORE_MARGIN) 3.8
set ::env(FP_CORE_UTIL) 80
set ::env(RUN_MAGIC) 1
set ::env(RUN_SIMPLE_CTS) 0
set ::env(FILL_INSERTION) 0
set ::env(SYNTH_BUFFERING) 0
set ::env(CELL_PAD) 0
set ::env(PLACE_SITE) unithv_double

set ::env(FP_IO_VEXTEND) 4
set ::env(FP_IO_HEXTEND) 4
set ::env(FP_IO_VTHICKNESS_MULT) 4
set ::env(FP_IO_HTHICKNESS_MULT) 4