| set ::env(DESIGN_NAME) "serv_top" | |
| set ::env(VERILOG_FILES) [glob ./designs/serv_top/src/*.v] | |
| set ::env(CLOCK_PERIOD) "10.000" | |
| set ::env(CLOCK_PORT) "clk" | |
| set ::env(FP_CORE_MARGIN) 3.36 | |
| set ::env(GLB_RT_ADJUSTMENT) 0.15 | |
| set ::env(SYNTH_STRATEGY) 0 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) |