designs/openfpga/config.tcl

# User config
set ::env(DESIGN_NAME) openfpga 

# Change if needed
set ::env(VERILOG_FILES) [glob ./designs/openfpga/src/*.v]

# Fill this
set ::env(CLOCK_PERIOD) "10"
set ::env(CLOCK_PORT) "clk_i"

set ::env(FP_CORE_UTIL) 40
set ::env(PL_TARGET_DENSITY) 0.4
set ::env(CLOCK_NET) $::env(CLOCK_PORT)