designs/md5/config.tcl

set ::env(DESIGN_NAME) "md5"

set ::env(VERILOG_FILES) "./designs/md5/src/md5.v"
set ::env(SDC_FILE) "./designs/md5/src/md5.sdc"

set ::env(CLOCK_PERIOD) "14"
set ::env(CLOCK_PORT) "clk"

set ::env(FP_CORE_MARGIN) 3.36
set ::env(GLB_RT_ADJUSTMENT) 0.1
set ::env(SYNTH_STRAT) 2
set ::env(CLOCK_NET) $::env(CLOCK_PORT)