| set ::env(DESIGN_NAME) "aes192" | |
| set ::env(VERILOG_FILES) "./designs/aes192/src/aes192.v" | |
| set ::env(SDC_FILE) "./designs/aes192/src/aes192.sdc" | |
| set ::env(CLOCK_PERIOD) "15.0" | |
| set ::env(CLOCK_PORT) "clk" | |
| set ::env(FP_CORE_MARGIN) 3.36 | |
| set ::env(GLB_RT_ADJUSTMENT) 0.1 | |
| set ::env(SYNTH_STRATEGY) 2 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) | |
| set ::env(FP_CORE_UTIL) 40 | |
| set ::env(PL_TARGET_DENSITY) 0.2 |