| set ::env(DESIGN_NAME) "APU" | |
| set ::env(VERILOG_FILES) "./designs/APU/src/APU.v" | |
| set ::env(CLOCK_PERIOD) "10.000" | |
| set ::env(CLOCK_PORT) "clk" | |
| set ::env(PL_TARGET_DENSITY) 0.5 | |
| set ::env(FP_CORE_UTIL) 40 | |
| set ::env(SYNTH_STRATEGY) 2 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) |