designs/striVe_chipcore/src/verilog/scs8hd.v

(* blackbox *)
module scs8hd_conb_1(output HI, output LO); endmodule
(* blackbox *)
module scs8hd_buf_8(input A, output X); endmodule
(* blackbox *)
module scs8hd_inv_8 (input A, output Y); endmodule