| set ::env(DESIGN_NAME) "sha512" | |
| set ::env(VERILOG_FILES) "./designs/sha512/src/sha512.v" | |
| set ::env(SDC_FILE) "./designs/sha512/src/$::env(DESIGN_NAME).sdc" | |
| set ::env(CLOCK_PERIOD) "10.000" | |
| set ::env(CLOCK_PORT) "clk" | |
| set ::env(FP_CORE_UTIL) 40 | |
| set ::env(PL_TARGET_DENSITY) 0.2 | |
| set ::env(GLB_RT_ADJUSTMENT) 0.15 | |
| set ::env(CTS_TOLERANCE) 500 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) |