designs/striVe/src/verilog/s8iom0s8.v

(* blackbox *)
module s8iom0s8_top_gpio_ovtv2 ( in, in_h, tie_hi_esd, tie_lo_esd, amuxbus_a,
    amuxbus_b, pad, pad_a_esd_0_h, pad_a_esd_1_h, pad_a_noesd_h, 
`ifdef USE_PG_PIN    
    vccd, vcchib,vdda, vddio, vddio_q, vssa, vssd, vssio, vssio_q, vswitch, 
`endif    
    analog_en, analog_pol, analog_sel, dm, enable_h, enable_inp_h, enable_vdda_h, enable_vddio, enable_vswitch_h, hld_h_n,
    hld_ovr, ib_mode_sel, inp_dis, oe_n, out, slow, slew_ctl, vtrip_sel, hys_trim, vinref );

   
input out;  		
input oe_n;  		
input hld_h_n;		
input enable_h;
input enable_inp_h;	
input enable_vdda_h;	
input enable_vddio;	
input enable_vswitch_h;	
input inp_dis;		
input vtrip_sel;	
input hys_trim;
input slow;
input [1:0] slew_ctl;		
input hld_ovr;		
input analog_en;	
input analog_sel;	
input analog_pol;	
input [2:0] dm;		
input [1:0] ib_mode_sel;
input vinref;


`ifdef USE_PG_PIN
	inout vddio;	
	inout vddio_q;	
	inout vdda;
	inout vccd;
	inout vswitch;
	inout vcchib;
	inout vssa;
	inout vssd;
	inout vssio_q;
	inout vssio;
`endif

inout pad;
inout pad_a_noesd_h,pad_a_esd_0_h,pad_a_esd_1_h;
inout amuxbus_a;
inout amuxbus_b;

output in;
output in_h;
output tie_hi_esd, tie_lo_esd;

endmodule


(* blackbox *)
module s8iom0s8_top_xres4v2 ( tie_weak_hi_h,  xres_h_n, tie_hi_esd, tie_lo_esd,
    amuxbus_a, amuxbus_b, pad, pad_a_esd_h, enable_h, en_vddio_sig_h, inp_sel_h, filt_in_h,
    disable_pullup_h, pullup_h, enable_vddio
`ifdef USE_PG_PIN    
    ,vccd, vcchib, vdda, vddio,vddio_q, vssa, vssd, vssio, vssio_q, vswitch
`endif   
     );

    output xres_h_n;
    inout amuxbus_a;
    inout amuxbus_b;
    inout pad;
    input disable_pullup_h;
    input enable_h; 
    input en_vddio_sig_h; 
    input inp_sel_h; 
    input filt_in_h;
    inout pullup_h;
    input enable_vddio;
    
`ifdef USE_PG_PIN 
    
    input vccd;
    input vcchib;
    input vdda;
    input vddio;
    input vddio_q;
    input vssa;
    input vssd;
    input vssio;
    input vssio_q;
    input vswitch;
    
    
    
`endif
    
    inout pad_a_esd_h;
    output tie_hi_esd;
    output tie_lo_esd;
    inout tie_weak_hi_h;
endmodule