designs/striVe_toplevel/src/verilog/digital_pll.v

(* blackbox *)
module digital_pll(reset, osc, clockp, clockd, div);

    input	reset;		// Sense positive reset
    input	osc;		// Input oscillator to match
    input [4:0]	div;		// PLL feedback division ratio

    output [1:0] clockp;	// Two 90 degree clock phases
    output [3:0] clockd;	// Divided clock (2, 4, 8, 16)
endmodule