designs/striVe_toplevel/src/striVe_spi.v

(* blackbox *)
module striVe_spi(
`ifdef LVS
	vdd, vss,
`endif
	RSTB, SCK, SDI, CSB, SDO, sdo_enb,
	xtal_ena, reg_ena, pll_vco_ena, pll_cp_ena, pll_bias_ena,
	pll_trim, pll_bypass, irq, reset, RST, trap,
	mfgr_id, prod_id, mask_rev_in, mask_rev);

`ifdef LVS
    inout vdd;	    // 3.3V supply
    inout vss;	    // common ground
`endif

    input RSTB;	    // 3.3V domain
    input SCK;	    // 3.3V domain
    input SDI;	    // 3.3V domain
    input CSB;	    // 3.3V domain
    output SDO;	    // 3.3V domain
    output sdo_enb;
    output xtal_ena;
    output reg_ena;
    output pll_vco_ena;
    output pll_cp_ena;
    output pll_bias_ena;
    output [3:0] pll_trim;
    output pll_bypass;
    output irq;
    output reset;
    output RST;
    input  trap;
    input [3:0] mask_rev_in;	// metal programmed;  3.3V domain
    output [11:0] mfgr_id;
    output [7:0] prod_id;
    output [3:0] mask_rev;
endmodule	// striVe_spi_orig