| // Digital PLL (ring oscillator + controller) |
| // Technically this is a frequency locked loop, not a phase locked loop. |
| |
| //`include "cells.v" |
| //`include "digital_pll_controller.v" |
| //`include "ring_osc2x13.v" |
| |
| |
| (* blackbox *) |
| module digital_pll(reset, osc, clockp, clockd, div); |
| |
| input reset; // Sense positive reset |
| input osc; // Input oscillator to match |
| input [4:0] div; // PLL feedback division ratio |
| |
| output [1:0] clockp; // Two 90 degree clock phases |
| output [3:0] clockd; // Divided clock (2, 4, 8, 16) |
| endmodule |
| |
