| set ::env(DESIGN_NAME) "point_add" | |
| set ::env(VERILOG_FILES) [glob ./designs/$::env(DESIGN_NAME)/src/*.v] | |
| set ::env(CLOCK_PERIOD) "5.000" | |
| set ::env(CLOCK_PORT) "clk" | |
| set ::env(GLB_RT_ADJUSTMENT) 0.15 | |
| set ::env(SYNTH_STRAT) 2 | |
| set ::env(FP_CORE_UTIL) 40 | |
| set ::env(PL_TARGET_DENSITY) 0.4 | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) |