| # Design | |
| set ::env(DESIGN_NAME) "aes_core" | |
| set ::env(VERILOG_FILES) "./designs/aes_core/src/aes.v" | |
| set ::env(CLOCK_PERIOD) "5.000" | |
| set ::env(CLOCK_PORT) "clk" | |
| set ::env(CLOCK_NET) $::env(CLOCK_PORT) | |
| # Regression | |
| set ::env(SYNTH_MAX_FANOUT) 6 | |
| set ::env(SYNTH_STRATEGY) 2 | |
| set ::env(PL_TARGET_DENSITY) 0.4 | |
| set ::env(FP_CORE_UTIL) 40 | |
| set ::env(FP_PDN_VPITCH) 153.6 | |
| set ::env(FP_PDN_HPITCH) 153.18 | |
| set ::env(FP_ASPECT_RATIO) 1 | |
| set ::env(GLB_RT_ADJUSTMENT) 0.2 | |
| # Extra | |
| set ::env(FILL_INSERTION) 1 | |