designs/striVe_chip/config.tcl

# User config
set ::env(DESIGN_NAME) striVe

# Change if needed
set ::env(VERILOG_FILES) "./designs/striVe_chip/src/verilog/src_routing.v"

# Fill this
set ::env(CLOCK_PERIOD) "50"
set ::env(CLOCK_PORT) "xclk"

set ::env(USE_GPIO_PADS) 1
set ::env(RUN_SIMPLE_CTS) 0
set ::env(FILL_INSERTION) 0
set ::env(SYNTH_TOP_LEVEL) 1
set ::env(CELL_PAD) 0
set ::env(MAGIC_PAD) 0
set ::env(MAGIC_ZEROIZE_ORIGIN) 0

set ::env(EXTRA_LEFS) [glob $::env(DESIGN_DIR)/src/mag/*.lef]
set ::env(EXTRA_GDS_FILES) [glob $::env(DESIGN_DIR)/src/mag/*.gds]