| lef ${MERGED_LEF} | |
| path ${CTS_DEF_INPUT} | |
| verilog ${CTS_VERILOG_INPUT} | |
| design ${DESIGN_NAME} | |
| target_skew ${CTS_TARGET_SKEW} | |
| tech 130 | |
| width ${CORE_WIDTH} | |
| height ${CORE_HEIGHT} | |
| ck_port ${CLOCK_PORT} | |
| db_units ${DEF_UNITS_PER_MICRON} | |
| root_buff ${CTS_ROOT_BUFFER} | |
| toler ${CTS_TOLER} | |
| percentile ${CTS_PERCENTILE} |