designs/usb/base_config.tcl

set ::env(DESIGN_NAME) "usb"

set ::env(VERILOG_FILES) "./designs/usb/src/usb2p0_core.v"

set ::env(CLOCK_PERIOD) "15.000"
set ::env(CLOCK_PORT) "clk_48"
set ::env(SYNTH_STRATEGY)    2