designs/aes_core/base_config.tcl

set ::env(DESIGN_NAME) "aes_core"

set ::env(VERILOG_FILES) "./designs/aes_core/src/aes.v"
set ::env(SDC_FILE) "./designs/$::env(DESIGN_NAME)/src/$::env(DESIGN_NAME).sdc"

set ::env(CLOCK_PERIOD) "5.000"
set ::env(CLOCK_PORT) "clk"