designs/CPU_CV/base_config.tcl

set ::env(DESIGN_NAME) "CPU"

set ::env(VERILOG_FILES) [glob ./designs/CPU_CV/src/*.v]
set ::env(SDC_FILE) "./designs/CPU_CV/src/CPU.sdc"

set ::env(CLOCK_PERIOD) "15.000"
set ::env(CLOCK_PORT) "clk"