| /*----------------------------------------------------------*/ |
| /* striVe, a raven/ravenna-like architecture in SkyWater s8 */ |
| /* */ |
| /* 1st edition, test of SkyWater s8 process */ |
| /* This version is missing all analog functionality, */ |
| /* including crystal oscillator, voltage regulator, and PLL */ |
| /* For simplicity, the pad arrangement of Raven has been */ |
| /* retained, even though many pads have no internal */ |
| /* connection. */ |
| /* */ |
| /* This version uses custom open-source standard cell and */ |
| /* I/O libraries. */ |
| /* */ |
| /* Copyright 2020 efabless, Inc. */ |
| /* Written by Tim Edwards, December 2019 */ |
| /* This file is open source hardware released under the */ |
| /* Apache 2.0 license. See file LICENSE. */ |
| /* */ |
| /* Library efs8_pads, Copyright 2020 efabless, Inc. */ |
| /*----------------------------------------------------------*/ |
| |
| `timescale 1 ns / 1 ps |
| //`default_nettype none |
| |
| /* Always define USE_PG_PIN (used by SkyWater cells) */ |
| `define USE_PG_PIN |
| |
| /* Define LVS (equivalent to USE_PG_PIN, used by qflow) */ |
| /* `define LVS */ |
| |
| /* Must define functional for now because otherwise the timing delays */ |
| /* are assumed, but they have been stripped out because some are not */ |
| /* parsed by iverilog. */ |
| |
| // `define functional |
| |
| // PDK IP |
| // Digital standard cells (to be changed to open-source library) |
| // `include "/ef/tech/SW/EFS8A/libs.ref/verilog/scs8ms/scs8ms.v" |
| |
| //`include "/home/tim/projects/efabless/tech/SkyWater/EFS8A/libs.ref/verilog/scs8ms/scs8ms.v" |
| |
| // I/O padframe cells |
| // `include "/ef/tech/SW/EFS8A/libs.ref/verilog/efs8_pads/efs8_pads.v" |
| |
| //`include "/home/tim/projects/efabless/tech/SkyWater/EFS8A/libs.ref/verilog/efs8_pads/efs8_pads.v" |
| |
| // Core cells, synthesized versions |
| // `include "openstriVe_soc/openstriVe_soc.v" |
| // `include "striVe_spi/striVe_spi.v" |
| // `include "digital_pll/digital_pll.v" |
| |
| // Core cells, functional source versions |
| (* blackbox *) |
| module striVe_ChipCore_ ( |
| `ifdef LVS |
| inout vdd1v8, /* 1.8V domain */ |
| inout vss, |
| `endif |
| // |
| //input pll_clk_core, |
| input ext_clk_core, |
| //input ext_clk_sel_core, |
| //input ext_reset, |
| //input reset, |
| |
| // Memory mapped I/O signals |
| input [0:15] gpio_out_core, // Connect to out on gpio pad |
| input [0:15] gpio_in_core, // Connect to in on gpio pad |
| output [0:15] gpio_pullupb_core, // Connect to pullupb on gpio pad |
| output [0:15] gpio_pulldownb_core, // Connect to pulldownb on gpio pad |
| output [0:15] gpio_outenb_core, // Connect to outenb on gpio pad |
| |
| // output adc0_ena_core, |
| // output adc0_convert_core, |
| // input [9:0] adc0_data_core, |
| // input adc0_done_core, |
| // output adc0_clk_core, |
| // output [1:0] adc0_inputsrc_core, |
| // output adc1_ena_core, |
| // output adc1_convert_core, |
| // output adc1_clk_core, |
| // output [1:0] adc1_inputsrc_core, |
| // input [9:0] adc1_data_core, |
| // input adc1_done_core, |
| // |
| // output dac_ena_core, |
| // output [9:0] dac_value_core, |
| // |
| // output analog_out_sel_core, // Analog output select (DAC or bandgap) |
| // output opamp_ena_core, // Op-amp enable for analog output |
| // output opamp_bias_ena_core, // Op-amp bias enable for analog output |
| // output bg_ena_core, // Bandgap enable |
| // |
| // output comp_ena, |
| // output [1:0] comp_ninputsrc, |
| // output [1:0] comp_pinputsrc, |
| // output rcosc_ena, |
| // |
| // output overtemp_ena, |
| // input overtemp, |
| // input rcosc_in, // RC oscillator output |
| // input xtal_in, // crystal oscillator output |
| // input comp_in, // comparator output |
| // input spi_sck, |
| |
| //input [7:0] spi_ro_config, |
| //input spi_ro_xtal_ena, |
| //input spi_ro_reg_ena, |
| //input spi_ro_pll_cp_ena, |
| //input spi_ro_pll_vco_ena, |
| //input spi_ro_pll_bias_ena, |
| //input [3:0] spi_ro_pll_trim, |
| |
| //input [11:0] spi_ro_mfgr_id, |
| //input [7:0] spi_ro_prod_id, |
| //input [3:0] spi_ro_mask_rev, |
| |
| // |
| input ser_tx_core, |
| input ser_rx_core, |
| |
| // IRQ |
| // |
| input irq_pin_core, // dedicated IRQ pin |
| //input irq_spi, // IRQ from standalone SPI |
| |
| // trap |
| //output trap, |
| |
| // Flash memory control (SPI master) |
| input flash_csb_core, |
| input flash_clk_core, |
| |
| // input flash_csb_oeb_core, |
| // output flash_clk_oeb_core, |
| |
| input flash_io0_oeb_core, |
| input flash_io1_oeb_core, |
| input flash_io2_oeb_core, |
| input flash_io3_oeb_core, |
| |
| input flash_io0_do_core, |
| input flash_io1_do_core, |
| input flash_io2_do_core, |
| input flash_io3_do_core, |
| |
| input flash_io0_di_core, |
| input flash_io1_di_core, |
| input flash_io2_di_core, |
| input flash_io3_di_core, |
| |
| // IO Pads |
| // spi |
| input porb, |
| input SCK_core, |
| input SDI_core, |
| input CSB_core, |
| input SDO_core, |
| output SDO_enb, |
| |
| // pll |
| input pll_clk16, |
| input xi_core |
| |
| |
| ); |
| |
| // wire por; |
| // |
| // // SoC core |
| ///* |
| // wire [9:0] adc0_data_core; |
| // wire [1:0] adc0_inputsrc_core; |
| // wire [9:0] adc1_data_core; |
| // wire [1:0] adc1_inputsrc_core; |
| // wire [9:0] dac_value_core; |
| // wire [1:0] comp_ninputsrc_core; |
| // wire [1:0] comp_pinputsrc_core; |
| // wire [7:0] spi_ro_config_core; |
| // wire [3:0] spi_ro_pll_trim_core; |
| // wire [11:0] spi_ro_mfgr_id_core; |
| // wire [7:0] spi_ro_prod_id_core; |
| // wire [3:0] spi_ro_mask_rev_core; |
| //*/ |
| // openstriVe_soc core ( |
| //`ifdef LVS |
| // .vdd1v8(vdd1v8), |
| // .vss(vss), |
| //`endif |
| // .pll_clk(pll_clk_core), |
| // .ext_clk(ext_clk_core), |
| // .ext_clk_sel(ext_clk_sel_core), |
| // .ext_reset(ext_reset_core), |
| // .reset(por), |
| // .gpio_out(gpio_out_core), |
| // .gpio_in(gpio_in_core), |
| // .gpio_pullupb(gpio_pullupb_core), |
| // .gpio_pulldownb(gpio_pulldownb_core), |
| // .gpio_outenb(gpio_outenb_core), |
| // .adc0_ena(adc0_ena_core), |
| // .adc0_convert(adc0_convert_core), |
| // .adc0_data(adc0_data_core), |
| // .adc0_done(adc0_done_core), |
| // .adc0_clk(adc0_clk_core), |
| // .adc0_inputsrc(adc0_inputsrc_core), |
| // .adc1_ena(adc1_ena_core), |
| // .adc1_convert(adc1_convert_core), |
| // .adc1_clk(adc1_clk_core), |
| // .adc1_inputsrc(adc1_inputsrc_core), |
| // .adc1_data(adc1_data_core), |
| // .adc1_done(adc1_done_core), |
| // .dac_ena(dac_ena_core), |
| // .dac_value(dac_value_core), |
| // .analog_out_sel(analog_out_sel_core), |
| // .opamp_ena(opamp_ena_core), |
| // .opamp_bias_ena(opamp_bias_ena_core), |
| // .bg_ena(bg_ena_core), |
| // .comp_ena(comp_ena_core), |
| // .comp_ninputsrc(comp_ninputsrc_core), |
| // .comp_pinputsrc(comp_pinputsrc_core), |
| // .rcosc_ena(rcosc_ena_core), |
| // .overtemp_ena(overtemp_ena_core), |
| // .overtemp(overtemp_core), |
| // .rcosc_in(rcosc_in_core), |
| // .xtal_in(xtal_in_core), |
| // .comp_in(comp_in_core), |
| // .spi_sck(SCK_core), |
| // .spi_ro_config(spi_ro_config_core), |
| // .spi_ro_xtal_ena(spi_ro_xtal_ena_core), |
| // .spi_ro_reg_ena(spi_ro_reg_ena_core), |
| // .spi_ro_pll_cp_ena(spi_ro_pll_cp_ena_core), |
| // .spi_ro_pll_vco_ena(spi_ro_pll_vco_ena_core), |
| // .spi_ro_pll_bias_ena(spi_ro_pll_bias_ena_core), |
| // .spi_ro_pll_trim(spi_ro_pll_trim_core), |
| // .spi_ro_mfgr_id(spi_ro_mfgr_id_core), |
| // .spi_ro_prod_id(spi_ro_prod_id_core), |
| // .spi_ro_mask_rev(spi_ro_mask_rev_core), |
| // .ser_tx(ser_tx_core), |
| // .ser_rx(ser_rx_core), |
| // .irq_pin(irq_pin_core), |
| // .irq_spi(irq_spi_core), |
| // .trap(trap_core), |
| // .flash_csb(flash_csb_core), |
| // .flash_clk(flash_clk_core), |
| // .flash_csb_oeb(flash_csb_oeb_core), |
| // .flash_clk_oeb(flash_clk_oeb_core), |
| // .flash_io0_oeb(flash_io0_oeb_core), |
| // .flash_io1_oeb(flash_io1_oeb_core), |
| // .flash_io2_oeb(flash_io2_oeb_core), |
| // .flash_io3_oeb(flash_io3_oeb_core), |
| // .flash_io0_do(flash_io0_do_core), |
| // .flash_io1_do(flash_io1_do_core), |
| // .flash_io2_do(flash_io2_do_core), |
| // .flash_io3_do(flash_io3_do_core), |
| // .flash_io0_di(flash_io0_di_core), |
| // .flash_io1_di(flash_io1_di_core), |
| // .flash_io2_di(flash_io2_di_core), |
| // .flash_io3_di(flash_io3_di_core) |
| // ); |
| // |
| // // For the mask revision input, use an array of digital constant logic cells |
| // |
| // wire [3:0] mask_rev = 4'b0; |
| ///* |
| // scs8ms_conb_1 mask_rev_value [3:0] ( |
| //`ifdef LVS |
| // .vpwr(vdd1v8), |
| // .vpb(vdd1v8), |
| // .vnb(vss), |
| // .vgnd(vss), |
| //`endif |
| // .HI(), |
| // .LO(mask_rev) |
| // ); |
| //*/ |
| // // Housekeeping SPI (at 1.8V). |
| // |
| // striVe_spi housekeeping ( |
| //`ifdef LVS |
| // .vdd(vdd1v8), |
| // .vss(vss), |
| //`endif |
| // .RSTB(porb), |
| // .SCK(SCK_core), |
| // .SDI(SDI_core), |
| // .CSB(CSB_core), |
| // .SDO(SDO_core), |
| // .sdo_enb(SDO_enb), // NOTE: 1.8V domain |
| // .xtal_ena(spi_ro_xtal_ena_core), |
| // .reg_ena(spi_ro_reg_ena_core), |
| // .pll_vco_ena(spi_ro_pll_vco_ena_core), |
| // .pll_cp_ena(spi_ro_pll_cp_ena_core), |
| // .pll_bias_ena(spi_ro_pll_bias_ena_core), // Use bit for 5th trim value |
| // .pll_trim(spi_ro_pll_trim_core), // ADPLL trim (lower four bits) |
| // .pll_bypass(ext_clk_sel_core), |
| // .irq(irq_spi_core), |
| // .RST(por), |
| // .reset(ext_reset_core), |
| // .trap(trap_core), |
| // .mfgr_id(spi_ro_mfgr_id_core), |
| // .prod_id(spi_ro_prod_id_core), |
| // .mask_rev_in(mask_rev), |
| // .mask_rev(spi_ro_mask_rev_core) |
| // ); |
| // |
| // // On-board experimental digital PLL |
| // // Use xi_core, assumed to be a CMOS digital clock signal. xo_core |
| // // is used as an output and set from pll_clk16. |
| // |
| // digital_pll pll ( |
| //`ifdef LVS |
| // .vdd(vdd1v8), |
| // .vss(vss), |
| //`endif |
| // .reset(ext_clk_sel_core), |
| // .osc(xi_core), |
| // .clockp({pll_clk_core, pll_clk_core90}), |
| // .clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}), |
| // .div({spi_ro_pll_bias_ena_core, spi_ro_pll_trim_core}) |
| // ); |
| |
| endmodule |
| |
| module striVe (vdd, vdd1v8, vss, gpio, xi, xo, adc0_in, adc1_in, adc_high, adc_low, |
| comp_inn, comp_inp, RSTB, ser_rx, ser_tx, irq, SDO, SDI, CSB, SCK, |
| xclk, flash_csb, flash_clk, flash_io0, flash_io1, flash_io2, flash_io3); |
| |
| input vdd; |
| input vdd1v8; |
| input vss; |
| |
| inout [15:0] gpio; |
| input xi; // CMOS clock input, not a crystal |
| output xo; // divide-by-16 clock output |
| input adc0_in; |
| input adc1_in; |
| input adc_high; |
| input adc_low; |
| input comp_inn; |
| input comp_inp; |
| input RSTB; // NOTE: Replaces analog_out pin from raven chip |
| input ser_rx; |
| output ser_tx; |
| input irq; |
| output SDO; |
| input SDI; |
| input CSB; |
| input SCK; |
| input xclk; |
| output flash_csb; |
| output flash_clk; |
| output flash_io0; |
| output flash_io1; |
| output flash_io2; |
| output flash_io3; |
| |
| wire vdd, vdd1v8, vss; |
| |
| wire [15:0] gpio_out_core; |
| wire [15:0] gpio_in_core; |
| wire [15:0] gpio_pullupb_core; |
| wire [15:0] gpio_pulldownb_core; |
| wire [15:0] gpio_outenb_core; |
| |
| // Instantiate power cells for VDD3V3 domain (4 total) |
| |
| vdd3v3_pad vdd3v3pad [3:0] ( |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| // Instantiate power cells for VDD3V3 ESD domain (4 total) |
| |
| vddio_pad vddiopad [3:0] ( |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| // Instantiate the core voltage supply (since it is not generated on-chip) |
| // (1.8V) (4 total) |
| |
| vdd1v8_pad vdd1v8pad [7:0] ( |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| // Instantiate ground cells (4 total) |
| |
| vss_pad vsspad [3:0] ( |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| // Instantiate ground cells for ESD domain (3 total) |
| |
| vssio_pad vssiopad [2:0] ( |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| // Instantiate digital bidirectional cell |
| |
| // 37 instances: 16 general purpose digital, 2 for the crystal oscillator, |
| // 4 for the ADC, 1 for the analog out, 2 for the comparator inputs, |
| // one for the IRQ input, one for the xclk input, 6 for the SPI flash |
| // signals, and 4 for the housekeeping SPI signals. |
| |
| // GPIO pads |
| digital_out_pad gpio_pad [15:0] ( |
| .out(gpio_out_core), // Signal from core to pad |
| .outenb(gpio_outenb_core), // Output enable (sense inverted) |
| .pulldownb(gpio_pulldownb_core), |
| .pullupb(gpio_pullupb_core), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss), |
| .PAD(gpio), |
| .in(gpio_in_core), // Signal from pad to core |
| .in3v() // VDDA domain signal (unused) |
| ); |
| |
| digital_in_pad xi_pad ( |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss), |
| .PAD(xi), |
| .in(xi_core), // Signal from pad to core |
| .in3v() // VDDA domain signal (unused) |
| ); |
| |
| digital_out_pad xo_pad ( |
| .out(pll_clk16), // Signal from core to pad |
| .outenb(vss), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss), |
| .PAD(xo), |
| .in(), // Signal from pad to core (unused) |
| .in3v() // VDDA domain signal (unused) |
| ); |
| |
| // analog200ohm_pad adc0_in_pad ( |
| // .VDDIO(vdd), |
| // .VDD3V3(vdd), |
| // .VDD1V8(vdd1v8), |
| // .VSS(vss), |
| // .VSSIO(vss), |
| // .PAD(adc0_in), |
| // .core(adc0_in_core) // Not used (yet) |
| // ); |
| // |
| // analog200ohm_pad adc1_in_pad ( |
| // .VDDIO(vdd), |
| // .VDD3V3(vdd), |
| // .VDD1V8(vdd1v8), |
| // .VSS(vss), |
| // .VSSIO(vss), |
| // .PAD(adc1_in), |
| // .core(adc1_in_core) // Not used (yet) |
| // ); |
| // |
| // analog_pad adc_high_pad ( |
| // .VDDIO(vdd), |
| // .VDD3V3(vdd), |
| // .VDD1V8(vdd1v8), |
| // .VSS(vss), |
| // .VSSIO(vss), |
| // .PAD(adc_high), |
| // .core(adc_high_core) // Not used (yet) |
| // ); |
| // |
| // analog_pad adc_low_pad ( |
| // .VDDIO(vdd), |
| // .VDD3V3(vdd), |
| // .VDD1V8(vdd1v8), |
| // .VSS(vss), |
| // .VSSIO(vss), |
| // .PAD(adc_low), |
| // .core(adc_low_core) // Not used (yet) |
| // ); |
| // |
| // analog200ohm_pad comp_inn_pad ( |
| // .VDDIO(vdd), |
| // .VDD3V3(vdd), |
| // .VDD1V8(vdd1v8), |
| // .VSS(vss), |
| // .VSSIO(vss), |
| // .PAD(comp_inn), |
| // .core(comp_inn_core) // Not used (yet) |
| // ); |
| // |
| // analog200ohm_pad comp_inp_pad ( |
| // .VDDIO(vdd), |
| // .VDD3V3(vdd), |
| // .VDD1V8(vdd1v8), |
| // .VSS(vss), |
| // .VSSIO(vss), |
| // .PAD(comp_inp), |
| // .core(comp_inp_core) // Not used (yet) |
| // ); |
| |
| // NOTE: The analog_out pad from the raven chip has been replaced by |
| // the digital reset input RSTB on striVe due to the lack of an on-board |
| // power-on-reset circuit. |
| |
| digital_in_pad RSTB_pad ( |
| .PAD(RSTB), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss), |
| .in(porb), // Signal from pad to core |
| .in3v(porb_h) // VDDA domain signal |
| ); |
| |
| digital_in_pad irq_pad ( |
| .PAD(irq), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss), |
| .in(irq_pin_core), // Signal from pad to core |
| .in3v() // VDDA domain signal (unused) |
| ); |
| |
| digital_out_pad SDO_pad ( |
| .out(SDO_core), // Signal from core to pad |
| .outenb(SDO_enb), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .in(), // Input (unused) |
| .in3v(), // VDD3V3 domain input (unused) |
| .PAD(SDO), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_in_pad SDI_pad ( |
| .in(SDI_core), // Signal from pad to core |
| .in3v(SDI_core_h), |
| .PAD(SDI), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_in_pad CSB_pad ( |
| .in(CSB_core), // Signal from pad to core |
| .in3v(CSB_core_h), |
| .PAD(CSB), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_in_pad SCK_pad ( |
| .in(SCK_core), // Signal from pad to core |
| .in3v(SCK_core_h), |
| .PAD(SCK), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_in_pad xclk_pad ( |
| .in(ext_clk_core), // Signal from pad to core |
| .in3v(), |
| .PAD(xclk), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_out_pad flash_csb_pad ( |
| .out(flash_csb_core), // Signal from core to pad |
| .outenb(vss), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .in(), // Input |
| .in3v(), // VDD3V3 domain input (unused) |
| .PAD(flash_csb), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_out_pad flash_clk_pad ( |
| .out(flash_clk_core), // Signal from core to pad |
| .outenb(vss), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .in(), // Input |
| .in3v(), // VDD3V3 domain input (unused) |
| .PAD(flash_clk), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_out_pad flash_io0_pad ( |
| .out(flash_io0_do_core), // Signal from core to pad |
| .outenb(flash_io0_oeb_core), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .in(flash_io0_di_core), // Input |
| .in3v(), // VDD3V3 domain input (unused) |
| .PAD(flash_io0), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_out_pad flash_io1_pad ( |
| .out(flash_io1_do_core), // Signal from core to pad |
| .outenb(flash_io1_oeb_core), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .in(flash_io1_di_core), // Input |
| .in3v(), // VDD3V3 domain input (unused) |
| .PAD(flash_io1), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_out_pad flash_io2_pad ( |
| .out(flash_io2_do_core), // Signal from core to pad |
| .outenb(flash_io2_oeb_core), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .in(flash_io2_di_core), // Input |
| .in3v(), // VDD3V3 domain input (unused) |
| .PAD(flash_io2), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_out_pad flash_io3_pad ( |
| .out(flash_io3_do_core), // Signal from core to pad |
| .outenb(flash_io3_oeb_core), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .in(flash_io3_di_core), // Input |
| .in3v(), // VDD3V3 domain input (unused) |
| .PAD(flash_io3), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_in_pad ser_rx_pad ( |
| .in(ser_rx_core), // Signal from pad to core |
| .in3v(), |
| .PAD(ser_rx), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| digital_out_pad ser_tx_pad ( |
| .out(ser_tx_core), // Signal from core to pad |
| .outenb(vss), // Output enable (sense inverted) |
| .pulldownb(vdd), |
| .pullupb(vdd), |
| .in(), // Input (unused) |
| .in3v(), // VDD3V3 domain input (unused) |
| .PAD(ser_tx), |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| // Corner cells |
| corner_pad corner [3:0] ( |
| .VDDIO(vdd), |
| .VDD3V3(vdd), |
| .VDD1V8(vdd1v8), |
| .VSS(vss), |
| .VSSIO(vss) |
| ); |
| |
| // SoC core |
| |
| wire [9:0] adc0_data_core; |
| wire [1:0] adc0_inputsrc_core; |
| wire [9:0] adc1_data_core; |
| wire [1:0] adc1_inputsrc_core; |
| wire [9:0] dac_value_core; |
| wire [1:0] comp_ninputsrc_core; |
| wire [1:0] comp_pinputsrc_core; |
| wire [7:0] spi_ro_config_core; |
| wire [3:0] spi_ro_pll_trim_core; |
| wire [11:0] spi_ro_mfgr_id_core; |
| wire [7:0] spi_ro_prod_id_core; |
| wire [3:0] spi_ro_mask_rev_core; |
| |
| striVe_ChipCore_ chip_core ( |
| |
| `ifdef LVS |
| .vdd1v8(vdd1v8), |
| .vss(vss), |
| `endif |
| |
| // |
| //input pll_clk_core, |
| .ext_clk_core(ext_clk_core), |
| //input ext_clk_sel_core, |
| //input ext_reset, |
| //input reset, |
| |
| // Memory mapped I/O signals |
| .gpio_out_core(gpio_out_core), // Connect to out on gpio pad |
| .gpio_in_core(gpio_in_core), // Connect to in on gpio pad |
| .gpio_pullupb_core(gpio_pullupb_core), // Connect to pullupb on gpio pad |
| .gpio_pulldownb_core(gpio_pulldownb_core), // Connect to pulldownb on gpio pad |
| .gpio_outenb_core(gpio_outenb_core), // Connect to outenb on gpio pad |
| |
| // .adc0_ena_core(adc0_ena_core), |
| // .adc0_convert_core(adc0_convert_core), |
| // .adc0_data_core(adc0_data_core), |
| // .adc0_done_core(adc0_done_core), |
| // .adc0_clk_core(adc0_clk_core), |
| // .adc0_inputsrc_core(adc0_inputsrc_core), |
| // .adc1_ena_core(adc1_ena_core), |
| // .adc1_convert_core(adc1_convert_core), |
| // .adc1_clk_core(adc1_clk_core), |
| // .adc1_inputsrc_core(adc1_inputsrc_core), |
| // .adc1_data_core(adc1_data_core), |
| // .adc1_done_core(adc1_done_core), |
| // |
| // .dac_ena_core(dac_ena_core), |
| // .dac_value_core(dac_value_core), |
| // |
| // .analog_out_sel_core(analog_out_sel_core), // Analog output select (DAC or bandgap) |
| // .opamp_ena_core(opamp_ena_core), // Op-amp enable for analog output |
| // .opamp_bias_ena_core(opamp_bias_ena_core), // Op-amp bias enable for analog output |
| // .bg_ena_core(bg_ena_core), // Bandgap enable |
| // |
| // .comp_ena(comp_ena), |
| // .comp_ninputsrc(comp_ninputsrc), |
| // .comp_pinputsrc(comp_pinputsrc), |
| // .rcosc_ena(rcosc_ena), |
| // |
| // .overtemp_ena(overtemp_ena), |
| // .overtemp(overtemp), |
| // .rcosc_in(rcosc_in), // RC oscillator output |
| // .xtal_in(xtal_in), // crystal oscillator output |
| // .comp_in(comp_in), // comparator output |
| // .spi_sck(spi_sck), |
| |
| //input [7:0] spi_ro_config, |
| //input spi_ro_xtal_ena, |
| //input spi_ro_reg_ena, |
| //input spi_ro_pll_cp_ena, |
| //input spi_ro_pll_vco_ena, |
| //input spi_ro_pll_bias_ena, |
| //input [3:0] spi_ro_pll_trim, |
| |
| //input [11:0] spi_ro_mfgr_id, |
| //input [7:0] spi_ro_prod_id, |
| //input [3:0] spi_ro_mask_rev, |
| |
| // |
| .ser_tx_core(ser_tx_core), |
| .ser_rx_core(ser_rx_core), |
| |
| // IRQ |
| // |
| .irq_pin_core(irq_pin_core), // dedicated IRQ pin |
| //input irq_spi, // IRQ from standalone SPI |
| |
| // trap |
| //output trap, |
| |
| // Flash memory control (SPI master) |
| .flash_csb_core(flash_csb_core), |
| .flash_clk_core(flash_clk_core), |
| |
| // .flash_csb_oeb_core(flash_csb_oeb_core), |
| // .flash_clk_oeb_core(flash_clk_oeb_core), |
| |
| .flash_io0_oeb_core(flash_io0_oeb_core), |
| .flash_io1_oeb_core(flash_io1_oeb_core), |
| .flash_io2_oeb_core(flash_io2_oeb_core), |
| .flash_io3_oeb_core(flash_io3_oeb_core), |
| |
| .flash_io0_do_core(flash_io0_do_core), |
| .flash_io1_do_core(flash_io1_do_core), |
| .flash_io2_do_core(flash_io2_do_core), |
| .flash_io3_do_core(flash_io3_do_core), |
| |
| .flash_io0_di_core(flash_io0_di_core), |
| .flash_io1_di_core(flash_io1_di_core), |
| .flash_io2_di_core(flash_io2_di_core), |
| .flash_io3_di_core(flash_io3_di_core), |
| |
| // IO Pads |
| // spi |
| .porb(porb), |
| .SCK_core(SCK_core), |
| .SDI_core(SDI_core), |
| .CSB_core(CSB_core), |
| .SDO_core(SDO_core), |
| .SDO_enb(SDO_enb), |
| |
| // pll |
| .pll_clk16(pll_clk16), |
| .xi_core(xi_core) |
| |
| |
| ); |
| endmodule |
| |
| module striVe_ChipCore ( |
| `ifdef LVS |
| inout vdd1v8, /* 1.8V domain */ |
| inout vss, |
| `endif |
| // |
| //input pll_clk_core, |
| input ext_clk_core, |
| //input ext_clk_sel_core, |
| //input ext_reset, |
| //input reset, |
| |
| // Memory mapped I/O signals |
| input [0:15] gpio_out_core, // Connect to out on gpio pad |
| input [0:15] gpio_in_core, // Connect to in on gpio pad |
| output [0:15] gpio_pullupb_core, // Connect to pullupb on gpio pad |
| output [0:15] gpio_pulldownb_core, // Connect to pulldownb on gpio pad |
| output [0:15] gpio_outenb_core, // Connect to outenb on gpio pad |
| |
| // output adc0_ena_core, |
| // output adc0_convert_core, |
| // input [9:0] adc0_data_core, |
| // input adc0_done_core, |
| // output adc0_clk_core, |
| // output [1:0] adc0_inputsrc_core, |
| // output adc1_ena_core, |
| // output adc1_convert_core, |
| // output adc1_clk_core, |
| // output [1:0] adc1_inputsrc_core, |
| // input [9:0] adc1_data_core, |
| // input adc1_done_core, |
| // |
| // output dac_ena_core, |
| // output [9:0] dac_value_core, |
| // |
| // output analog_out_sel_core, // Analog output select (DAC or bandgap) |
| // output opamp_ena_core, // Op-amp enable for analog output |
| // output opamp_bias_ena_core, // Op-amp bias enable for analog output |
| // output bg_ena_core, // Bandgap enable |
| // |
| // output comp_ena, |
| // output [1:0] comp_ninputsrc, |
| // output [1:0] comp_pinputsrc, |
| // output rcosc_ena, |
| // |
| // output overtemp_ena, |
| // input overtemp, |
| // input rcosc_in, // RC oscillator output |
| // input xtal_in, // crystal oscillator output |
| // input comp_in, // comparator output |
| // input spi_sck, |
| |
| //input [7:0] spi_ro_config, |
| //input spi_ro_xtal_ena, |
| //input spi_ro_reg_ena, |
| //input spi_ro_pll_cp_ena, |
| //input spi_ro_pll_vco_ena, |
| //input spi_ro_pll_bias_ena, |
| //input [3:0] spi_ro_pll_trim, |
| |
| //input [11:0] spi_ro_mfgr_id, |
| //input [7:0] spi_ro_prod_id, |
| //input [3:0] spi_ro_mask_rev, |
| |
| // |
| input ser_tx_core, |
| input ser_rx_core, |
| |
| // IRQ |
| // |
| input irq_pin_core, // dedicated IRQ pin |
| //input irq_spi, // IRQ from standalone SPI |
| |
| // trap |
| //output trap, |
| |
| // Flash memory control (SPI master) |
| input flash_csb_core, |
| input flash_clk_core, |
| |
| // input flash_csb_oeb_core, |
| // output flash_clk_oeb_core, |
| |
| input flash_io0_oeb_core, |
| input flash_io1_oeb_core, |
| input flash_io2_oeb_core, |
| input flash_io3_oeb_core, |
| |
| input flash_io0_do_core, |
| input flash_io1_do_core, |
| input flash_io2_do_core, |
| input flash_io3_do_core, |
| |
| input flash_io0_di_core, |
| input flash_io1_di_core, |
| input flash_io2_di_core, |
| input flash_io3_di_core, |
| |
| // IO Pads |
| // spi |
| input porb, |
| input SCK_core, |
| input SDI_core, |
| input CSB_core, |
| input SDO_core, |
| output SDO_enb, |
| |
| // pll |
| input pll_clk16, |
| input xi_core |
| |
| |
| ); |
| |
| wire por; |
| |
| // SoC core |
| /* |
| wire [9:0] adc0_data_core; |
| wire [1:0] adc0_inputsrc_core; |
| wire [9:0] adc1_data_core; |
| wire [1:0] adc1_inputsrc_core; |
| wire [9:0] dac_value_core; |
| wire [1:0] comp_ninputsrc_core; |
| wire [1:0] comp_pinputsrc_core; |
| wire [7:0] spi_ro_config_core; |
| wire [3:0] spi_ro_pll_trim_core; |
| wire [11:0] spi_ro_mfgr_id_core; |
| wire [7:0] spi_ro_prod_id_core; |
| wire [3:0] spi_ro_mask_rev_core; |
| */ |
| openstriVe_soc core ( |
| `ifdef LVS |
| .vdd1v8(vdd1v8), |
| .vss(vss), |
| `endif |
| .pll_clk(pll_clk_core), |
| .ext_clk(ext_clk_core), |
| .ext_clk_sel(ext_clk_sel_core), |
| .ext_reset(ext_reset_core), |
| .reset(por), |
| .gpio_out(gpio_out_core), |
| .gpio_in(gpio_in_core), |
| .gpio_pullupb(gpio_pullupb_core), |
| .gpio_pulldownb(gpio_pulldownb_core), |
| .gpio_outenb(gpio_outenb_core), |
| // .adc0_ena(adc0_ena_core), |
| // .adc0_convert(adc0_convert_core), |
| // .adc0_data(adc0_data_core), |
| // .adc0_done(adc0_done_core), |
| // .adc0_clk(adc0_clk_core), |
| // .adc0_inputsrc(adc0_inputsrc_core), |
| // .adc1_ena(adc1_ena_core), |
| // .adc1_convert(adc1_convert_core), |
| // .adc1_clk(adc1_clk_core), |
| // .adc1_inputsrc(adc1_inputsrc_core), |
| // .adc1_data(adc1_data_core), |
| // .adc1_done(adc1_done_core), |
| // .dac_ena(dac_ena_core), |
| // .dac_value(dac_value_core), |
| // .analog_out_sel(analog_out_sel_core), |
| // .opamp_ena(opamp_ena_core), |
| // .opamp_bias_ena(opamp_bias_ena_core), |
| // .bg_ena(bg_ena_core), |
| // .comp_ena(comp_ena_core), |
| // .comp_ninputsrc(comp_ninputsrc_core), |
| // .comp_pinputsrc(comp_pinputsrc_core), |
| // .rcosc_ena(rcosc_ena_core), |
| // .overtemp_ena(overtemp_ena_core), |
| // .overtemp(overtemp_core), |
| // .rcosc_in(rcosc_in_core), |
| // .xtal_in(xtal_in_core), |
| // .comp_in(comp_in_core), |
| // .spi_sck(SCK_core), |
| .spi_ro_config(spi_ro_config_core), |
| .spi_ro_xtal_ena(spi_ro_xtal_ena_core), |
| .spi_ro_reg_ena(spi_ro_reg_ena_core), |
| .spi_ro_pll_cp_ena(spi_ro_pll_cp_ena_core), |
| .spi_ro_pll_vco_ena(spi_ro_pll_vco_ena_core), |
| .spi_ro_pll_bias_ena(spi_ro_pll_bias_ena_core), |
| .spi_ro_pll_trim(spi_ro_pll_trim_core), |
| .spi_ro_mfgr_id(spi_ro_mfgr_id_core), |
| .spi_ro_prod_id(spi_ro_prod_id_core), |
| .spi_ro_mask_rev(spi_ro_mask_rev_core), |
| .ser_tx(ser_tx_core), |
| .ser_rx(ser_rx_core), |
| .irq_pin(irq_pin_core), |
| .irq_spi(irq_spi_core), |
| .trap(trap_core), |
| .flash_csb(flash_csb_core), |
| .flash_clk(flash_clk_core), |
| // .flash_csb_oeb(flash_csb_oeb_core), |
| // .flash_clk_oeb(flash_clk_oeb_core), |
| .flash_io0_oeb(flash_io0_oeb_core), |
| .flash_io1_oeb(flash_io1_oeb_core), |
| .flash_io2_oeb(flash_io2_oeb_core), |
| .flash_io3_oeb(flash_io3_oeb_core), |
| .flash_io0_do(flash_io0_do_core), |
| .flash_io1_do(flash_io1_do_core), |
| .flash_io2_do(flash_io2_do_core), |
| .flash_io3_do(flash_io3_do_core), |
| .flash_io0_di(flash_io0_di_core), |
| .flash_io1_di(flash_io1_di_core), |
| .flash_io2_di(flash_io2_di_core), |
| .flash_io3_di(flash_io3_di_core) |
| ); |
| |
| // For the mask revision input, use an array of digital constant logic cells |
| |
| wire [3:0] mask_rev = 4'b0; |
| /* |
| scs8ms_conb_1 mask_rev_value [3:0] ( |
| `ifdef LVS |
| .vpwr(vdd1v8), |
| .vpb(vdd1v8), |
| .vnb(vss), |
| .vgnd(vss), |
| `endif |
| .HI(), |
| .LO(mask_rev) |
| ); |
| */ |
| // Housekeeping SPI (at 1.8V). |
| |
| striVe_spi housekeeping ( |
| `ifdef LVS |
| .vdd(vdd1v8), |
| .vss(vss), |
| `endif |
| .RSTB(porb), |
| .SCK(SCK_core), |
| .SDI(SDI_core), |
| .CSB(CSB_core), |
| .SDO(SDO_core), |
| .sdo_enb(SDO_enb), // NOTE: 1.8V domain |
| .xtal_ena(spi_ro_xtal_ena_core), |
| .reg_ena(spi_ro_reg_ena_core), |
| .pll_vco_ena(spi_ro_pll_vco_ena_core), |
| .pll_cp_ena(spi_ro_pll_cp_ena_core), |
| .pll_bias_ena(spi_ro_pll_bias_ena_core), // Use bit for 5th trim value |
| .pll_trim(spi_ro_pll_trim_core), // ADPLL trim (lower four bits) |
| .pll_bypass(ext_clk_sel_core), |
| .irq(irq_spi_core), |
| .RST(por), |
| .reset(ext_reset_core), |
| .trap(trap_core), |
| .mfgr_id(spi_ro_mfgr_id_core), |
| .prod_id(spi_ro_prod_id_core), |
| .mask_rev_in(mask_rev), |
| .mask_rev(spi_ro_mask_rev_core) |
| ); |
| |
| // On-board experimental digital PLL |
| // Use xi_core, assumed to be a CMOS digital clock signal. xo_core |
| // is used as an output and set from pll_clk16. |
| |
| digital_pll pll ( |
| `ifdef LVS |
| .vdd(vdd1v8), |
| .vss(vss), |
| `endif |
| .reset(ext_clk_sel_core), |
| .osc(xi_core), |
| .clockp({pll_clk_core, pll_clk_core90}), |
| .clockd({pll_clk2, pll_clk4, pll_clk8, pll_clk16}), |
| .div({spi_ro_pll_bias_ena_core, spi_ro_pll_trim_core}) |
| ); |
| |
| endmodule |
| |
| |
