| Qflow synthesis logfile created on Thu Feb 27 08:46:16 PST 2020 |
| Running yosys for verilog parsing and synthesis |
| yosys -s ring_osc2x13.ys |
| |
| /----------------------------------------------------------------------------\ |
| | | |
| | yosys -- Yosys Open SYnthesis Suite | |
| | | |
| | Copyright (C) 2012 - 2018 Clifford Wolf <clifford@clifford.at> | |
| | | |
| | Permission to use, copy, modify, and/or distribute this software for any | |
| | purpose with or without fee is hereby granted, provided that the above | |
| | copyright notice and this permission notice appear in all copies. | |
| | | |
| | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| | | |
| \----------------------------------------------------------------------------/ |
| |
| Yosys 0.8+17 (git sha1 11c8a9eb, gcc 4.7.4 -fPIC -Os) |
| |
| |
| -- Executing script file `ring_osc2x13.ys' -- |
| |
| 1. Executing Liberty frontend. |
| Imported 428 cell types from liberty file. |
| |
| 2. Executing Verilog-2005 frontend. |
| Parsing Verilog input from `/home/tim/gits/openstriVe/qflow/ring_osc2x13/source/ring_osc2x13.v' to AST representation. |
| Generating RTLIL representation for module `\delay_stage'. |
| /home/tim/gits/openstriVe/qflow/ring_osc2x13/source/ring_osc2x13.v:15: Warning: Identifier `\ts' is implicitly declared. |
| Generating RTLIL representation for module `\start_stage'. |
| Generating RTLIL representation for module `\ring_osc2x13'. |
| Successfully finished Verilog frontend. |
| |
| 3. Executing SYNTH pass. |
| |
| 3.1. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 3.1.1. Analyzing design hierarchy.. |
| Top module: \ring_osc2x13 |
| Used module: \delay_stage |
| Used module: \start_stage |
| |
| 3.1.2. Analyzing design hierarchy.. |
| Top module: \ring_osc2x13 |
| Used module: \delay_stage |
| Used module: \start_stage |
| Removed 0 unused modules. |
| |
| 3.2. Executing PROC pass (convert processes to netlists). |
| |
| 3.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 3.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). |
| Removed a total of 0 dead cases. |
| |
| 3.2.3. Executing PROC_INIT pass (extract init attributes). |
| |
| 3.2.4. Executing PROC_ARST pass (detect async resets in processes). |
| |
| 3.2.5. Executing PROC_MUX pass (convert decision trees to multiplexers). |
| |
| 3.2.6. Executing PROC_DLATCH pass (convert process syncs to latches). |
| |
| 3.2.7. Executing PROC_DFF pass (convert process syncs to FFs). |
| |
| 3.2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). |
| Cleaned up 0 empty switches. |
| |
| 3.3. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| Finding unused cells or wires in module \delay_stage.. |
| |
| 3.5. Executing CHECK pass (checking for obvious problems). |
| checking module delay_stage.. |
| Warning: multiple conflicting drivers for delay_stage.\d1: |
| port Z[0] of cell delayen1 (scs8hd_einvp_2) |
| port Z[0] of cell delayenb1 (scs8hd_einvn_4) |
| Warning: multiple conflicting drivers for delay_stage.\out: |
| port Z[0] of cell delayen0 (scs8hd_einvp_2) |
| port Z[0] of cell delayenb0 (scs8hd_einvn_8) |
| checking module ring_osc2x13.. |
| checking module start_stage.. |
| Warning: multiple conflicting drivers for start_stage.\d1: |
| port Z[0] of cell delayen1 (scs8hd_einvp_2) |
| port Z[0] of cell delayenb1 (scs8hd_einvn_4) |
| Warning: multiple conflicting drivers for start_stage.\out: |
| port Z[0] of cell delayen0 (scs8hd_einvp_2) |
| port Z[0] of cell delayenb0 (scs8hd_einvn_8) |
| port Z[0] of cell reseten0 (scs8hd_einvp_1) |
| found and reported 4 problems. |
| |
| 3.6. Executing OPT pass (performing simple optimizations). |
| |
| 3.6.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.6.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \delay_stage.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizer on module \ring_osc2x13.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizer on module \start_stage.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 3.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \delay_stage. |
| Optimizing cells in module \ring_osc2x13. |
| Optimizing cells in module \start_stage. |
| Performed a total of 0 changes. |
| |
| 3.6.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.6.6. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 3.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.6.8. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.6.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 3.7. Executing WREDUCE pass (reducing word size of cells). |
| |
| 3.8. Executing ALUMACC pass (create $alu and $macc cells). |
| Extracting $alu and $macc cells in module delay_stage: |
| created 0 $alu and 0 $macc cells. |
| Extracting $alu and $macc cells in module ring_osc2x13: |
| created 0 $alu and 0 $macc cells. |
| Extracting $alu and $macc cells in module start_stage: |
| created 0 $alu and 0 $macc cells. |
| |
| 3.9. Executing SHARE pass (SAT-based resource sharing). |
| |
| 3.10. Executing OPT pass (performing simple optimizations). |
| |
| 3.10.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.10.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \delay_stage.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizer on module \ring_osc2x13.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizer on module \start_stage.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \delay_stage. |
| Optimizing cells in module \ring_osc2x13. |
| Optimizing cells in module \start_stage. |
| Performed a total of 0 changes. |
| |
| 3.10.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.10.6. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.10.8. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.10.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 3.11. Executing FSM pass (extract and optimize FSM). |
| |
| 3.11.1. Executing FSM_DETECT pass (finding FSMs in design). |
| |
| 3.11.2. Executing FSM_EXTRACT pass (extracting FSM from design). |
| |
| 3.11.3. Executing FSM_OPT pass (simple optimizations of FSMs). |
| |
| 3.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.11.5. Executing FSM_OPT pass (simple optimizations of FSMs). |
| |
| 3.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). |
| |
| 3.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells). |
| |
| 3.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic). |
| |
| 3.12. Executing OPT pass (performing simple optimizations). |
| |
| 3.12.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.12.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.12.3. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 3.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.12.5. Finished fast OPT passes. |
| |
| 3.13. Executing MEMORY pass. |
| |
| 3.13.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). |
| |
| 3.13.2. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.13.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). |
| |
| 3.13.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.13.5. Executing MEMORY_COLLECT pass (generating $mem cells). |
| |
| 3.14. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.15. Executing OPT pass (performing simple optimizations). |
| |
| 3.15.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.15.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.15.3. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 3.15.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.15.5. Finished fast OPT passes. |
| |
| 3.16. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). |
| |
| 3.17. Executing OPT pass (performing simple optimizations). |
| |
| 3.17.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.17.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.17.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \delay_stage.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizer on module \ring_osc2x13.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizer on module \start_stage.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 3.17.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \delay_stage. |
| Optimizing cells in module \ring_osc2x13. |
| Optimizing cells in module \start_stage. |
| Performed a total of 0 changes. |
| |
| 3.17.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.17.6. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 3.17.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.17.8. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.17.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 3.18. Executing TECHMAP pass (map to technology primitives). |
| |
| 3.18.1. Executing Verilog-2005 frontend. |
| Parsing Verilog input from `<techmap.v>' to AST representation. |
| Generating RTLIL representation for module `\_90_simplemap_bool_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_logic_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_compare_ops'. |
| Generating RTLIL representation for module `\_90_simplemap_various'. |
| Generating RTLIL representation for module `\_90_simplemap_registers'. |
| Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. |
| Generating RTLIL representation for module `\_90_shift_shiftx'. |
| Generating RTLIL representation for module `\_90_fa'. |
| Generating RTLIL representation for module `\_90_lcu'. |
| Generating RTLIL representation for module `\_90_alu'. |
| Generating RTLIL representation for module `\_90_macc'. |
| Generating RTLIL representation for module `\_90_alumacc'. |
| Generating RTLIL representation for module `\$__div_mod_u'. |
| Generating RTLIL representation for module `\$__div_mod'. |
| Generating RTLIL representation for module `\_90_div'. |
| Generating RTLIL representation for module `\_90_mod'. |
| Generating RTLIL representation for module `\_90_pow'. |
| Generating RTLIL representation for module `\_90_pmux'. |
| Generating RTLIL representation for module `\_90_lut'. |
| Successfully finished Verilog frontend. |
| No more expansions possible. |
| |
| 3.19. Executing OPT pass (performing simple optimizations). |
| |
| 3.19.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.19.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.19.3. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 3.19.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.19.5. Finished fast OPT passes. |
| |
| 3.20. Executing ABC pass (technology mapping using ABC). |
| |
| 3.20.1. Extracting gate netlist of module `\delay_stage' to `<abc-temp-dir>/input.blif'.. |
| Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. |
| Don't call ABC as there is nothing to map. |
| Removing temp directory. |
| |
| 3.20.2. Extracting gate netlist of module `\ring_osc2x13' to `<abc-temp-dir>/input.blif'.. |
| Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. |
| Don't call ABC as there is nothing to map. |
| Removing temp directory. |
| |
| 3.20.3. Extracting gate netlist of module `\start_stage' to `<abc-temp-dir>/input.blif'.. |
| Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. |
| Don't call ABC as there is nothing to map. |
| Removing temp directory. |
| |
| 3.21. Executing OPT pass (performing simple optimizations). |
| |
| 3.21.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 3.21.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 3.21.3. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 3.21.4. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 3.21.5. Finished fast OPT passes. |
| |
| 3.22. Executing HIERARCHY pass (managing design hierarchy). |
| |
| 3.22.1. Analyzing design hierarchy.. |
| Top module: \ring_osc2x13 |
| Used module: \delay_stage |
| Used module: \start_stage |
| |
| 3.22.2. Analyzing design hierarchy.. |
| Top module: \ring_osc2x13 |
| Used module: \delay_stage |
| Used module: \start_stage |
| Removed 0 unused modules. |
| |
| 3.23. Printing statistics. |
| |
| === delay_stage === |
| |
| Number of wires: 7 |
| Number of wire bits: 8 |
| Number of public wires: 7 |
| Number of public wire bits: 8 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 7 |
| scs8hd_clkbuf_1 1 |
| scs8hd_clkbuf_2 1 |
| scs8hd_clkinv_1 1 |
| scs8hd_einvn_4 1 |
| scs8hd_einvn_8 1 |
| scs8hd_einvp_2 2 |
| |
| === ring_osc2x13 === |
| |
| Number of wires: 5 |
| Number of wire bits: 44 |
| Number of public wires: 5 |
| Number of public wire bits: 44 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 17 |
| delay_stage 12 |
| scs8hd_clkinv_2 2 |
| scs8hd_clkinv_8 2 |
| start_stage 1 |
| |
| === start_stage === |
| |
| Number of wires: 9 |
| Number of wire bits: 10 |
| Number of public wires: 9 |
| Number of public wire bits: 10 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 9 |
| scs8hd_clkbuf_1 1 |
| scs8hd_clkinv_1 1 |
| scs8hd_conb_1 1 |
| scs8hd_einvn_4 1 |
| scs8hd_einvn_8 1 |
| scs8hd_einvp_1 1 |
| scs8hd_einvp_2 2 |
| scs8hd_or2_2 1 |
| |
| === design hierarchy === |
| |
| ring_osc2x13 1 |
| delay_stage 12 |
| start_stage 1 |
| |
| Number of wires: 98 |
| Number of wire bits: 150 |
| Number of public wires: 98 |
| Number of public wire bits: 150 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 97 |
| scs8hd_clkbuf_1 13 |
| scs8hd_clkbuf_2 12 |
| scs8hd_clkinv_1 13 |
| scs8hd_clkinv_2 2 |
| scs8hd_clkinv_8 2 |
| scs8hd_conb_1 1 |
| scs8hd_einvn_4 13 |
| scs8hd_einvn_8 13 |
| scs8hd_einvp_1 1 |
| scs8hd_einvp_2 26 |
| scs8hd_or2_2 1 |
| |
| 3.24. Executing CHECK pass (checking for obvious problems). |
| checking module delay_stage.. |
| Warning: multiple conflicting drivers for delay_stage.\d1: |
| port Z[0] of cell delayen1 (scs8hd_einvp_2) |
| port Z[0] of cell delayenb1 (scs8hd_einvn_4) |
| Warning: multiple conflicting drivers for delay_stage.\out: |
| port Z[0] of cell delayen0 (scs8hd_einvp_2) |
| port Z[0] of cell delayenb0 (scs8hd_einvn_8) |
| checking module ring_osc2x13.. |
| checking module start_stage.. |
| Warning: multiple conflicting drivers for start_stage.\d1: |
| port Z[0] of cell delayen1 (scs8hd_einvp_2) |
| port Z[0] of cell delayenb1 (scs8hd_einvn_4) |
| Warning: multiple conflicting drivers for start_stage.\out: |
| port Z[0] of cell delayen0 (scs8hd_einvp_2) |
| port Z[0] of cell delayenb0 (scs8hd_einvn_8) |
| port Z[0] of cell reseten0 (scs8hd_einvp_1) |
| found and reported 4 problems. |
| |
| 4. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file). |
| cell scs8hd_dfxtp_1 (noninv, pins=3, area=20.02) is a direct match for cell type $_DFF_P_. |
| cell scs8hd_dfrtn_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_NN0_. |
| cell scs8hd_dfrtp_1 (noninv, pins=4, area=25.02) is a direct match for cell type $_DFF_PN0_. |
| cell scs8hd_dfstp_2 (noninv, pins=4, area=26.28) is a direct match for cell type $_DFF_PN1_. |
| cell scs8hd_dfbbn_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_NNN_. |
| cell scs8hd_dfbbp_1 (noninv, pins=6, area=32.53) is a direct match for cell type $_DFFSR_PNN_. |
| create mapping for $_DFF_NP0_ from mapping for $_DFF_NN0_. |
| create mapping for $_DFF_PP0_ from mapping for $_DFF_PN0_. |
| create mapping for $_DFF_PP1_ from mapping for $_DFF_PN1_. |
| create mapping for $_DFFSR_NPN_ from mapping for $_DFFSR_NNN_. |
| create mapping for $_DFFSR_PPN_ from mapping for $_DFFSR_PNN_. |
| create mapping for $_DFFSR_NNP_ from mapping for $_DFFSR_NNN_. |
| create mapping for $_DFFSR_NPP_ from mapping for $_DFFSR_NNP_. |
| create mapping for $_DFFSR_PNP_ from mapping for $_DFFSR_PNN_. |
| create mapping for $_DFFSR_PPP_ from mapping for $_DFFSR_PNP_. |
| create mapping for $_DFF_NN1_ from mapping for $_DFF_NN0_. |
| create mapping for $_DFF_NP1_ from mapping for $_DFF_NN1_. |
| create mapping for $_DFF_N_ from mapping for $_DFF_P_. |
| final dff cell mappings: |
| scs8hd_dfxtp_1 _DFF_N_ (.CLK(~C), .D( D), .Q( Q)); |
| scs8hd_dfxtp_1 _DFF_P_ (.CLK( C), .D( D), .Q( Q)); |
| scs8hd_dfrtn_1 _DFF_NN0_ (.CLKN( C), .D( D), .Q( Q), .RESETB( R)); |
| scs8hd_dfrtn_1 _DFF_NN1_ (.CLKN( C), .D(~D), .Q(~Q), .RESETB( R)); |
| scs8hd_dfrtn_1 _DFF_NP0_ (.CLKN( C), .D( D), .Q( Q), .RESETB(~R)); |
| scs8hd_dfrtn_1 _DFF_NP1_ (.CLKN( C), .D(~D), .Q(~Q), .RESETB(~R)); |
| scs8hd_dfrtp_1 _DFF_PN0_ (.CLK( C), .D( D), .Q( Q), .RESETB( R)); |
| scs8hd_dfstp_2 _DFF_PN1_ (.CLK( C), .D( D), .Q( Q), .SETB( R)); |
| scs8hd_dfrtp_1 _DFF_PP0_ (.CLK( C), .D( D), .Q( Q), .RESETB(~R)); |
| scs8hd_dfstp_2 _DFF_PP1_ (.CLK( C), .D( D), .Q( Q), .SETB(~R)); |
| scs8hd_dfbbn_1 _DFFSR_NNN_ (.CLKN( C), .D( D), .Q( Q), .QN(~Q), .RESETB( R), .SETB( S)); |
| scs8hd_dfbbn_1 _DFFSR_NNP_ (.CLKN( C), .D( D), .Q( Q), .QN(~Q), .RESETB(~R), .SETB( S)); |
| scs8hd_dfbbn_1 _DFFSR_NPN_ (.CLKN( C), .D( D), .Q( Q), .QN(~Q), .RESETB( R), .SETB(~S)); |
| scs8hd_dfbbn_1 _DFFSR_NPP_ (.CLKN( C), .D( D), .Q( Q), .QN(~Q), .RESETB(~R), .SETB(~S)); |
| scs8hd_dfbbp_1 _DFFSR_PNN_ (.CLK( C), .D( D), .Q( Q), .QN(~Q), .RESETB( R), .SETB( S)); |
| scs8hd_dfbbp_1 _DFFSR_PNP_ (.CLK( C), .D( D), .Q( Q), .QN(~Q), .RESETB(~R), .SETB( S)); |
| scs8hd_dfbbp_1 _DFFSR_PPN_ (.CLK( C), .D( D), .Q( Q), .QN(~Q), .RESETB( R), .SETB(~S)); |
| scs8hd_dfbbp_1 _DFFSR_PPP_ (.CLK( C), .D( D), .Q( Q), .QN(~Q), .RESETB(~R), .SETB(~S)); |
| Mapping DFF cells in module `\delay_stage': |
| Mapping DFF cells in module `\ring_osc2x13': |
| Mapping DFF cells in module `\start_stage': |
| |
| 5. Executing OPT pass (performing simple optimizations). |
| |
| 5.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 5.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \delay_stage.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizer on module \ring_osc2x13.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Running muxtree optimizer on module \start_stage.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \delay_stage. |
| Optimizing cells in module \ring_osc2x13. |
| Optimizing cells in module \start_stage. |
| Performed a total of 0 changes. |
| |
| 5.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\delay_stage'. |
| Finding identical cells in module `\ring_osc2x13'. |
| Finding identical cells in module `\start_stage'. |
| Removed a total of 0 cells. |
| |
| 5.6. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 5.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \delay_stage.. |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Finding unused cells or wires in module \start_stage.. |
| |
| 5.8. Executing OPT_EXPR pass (perform const folding). |
| |
| 5.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 6. Executing ABC pass (technology mapping using ABC). |
| |
| 6.1. Extracting gate netlist of module `\delay_stage' to `<abc-temp-dir>/input.blif'.. |
| Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. |
| Don't call ABC as there is nothing to map. |
| Removing temp directory. |
| |
| 6.2. Extracting gate netlist of module `\ring_osc2x13' to `<abc-temp-dir>/input.blif'.. |
| Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. |
| Don't call ABC as there is nothing to map. |
| Removing temp directory. |
| |
| 6.3. Extracting gate netlist of module `\start_stage' to `<abc-temp-dir>/input.blif'.. |
| Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. |
| Don't call ABC as there is nothing to map. |
| Removing temp directory. |
| |
| 7. Executing FLATTEN pass (flatten design). |
| Mapping ring_osc2x13.dstage[0].id using delay_stage. |
| Mapping ring_osc2x13.dstage[1].id using delay_stage. |
| Mapping ring_osc2x13.dstage[2].id using delay_stage. |
| Mapping ring_osc2x13.dstage[3].id using delay_stage. |
| Mapping ring_osc2x13.dstage[4].id using delay_stage. |
| Mapping ring_osc2x13.dstage[5].id using delay_stage. |
| Mapping ring_osc2x13.dstage[6].id using delay_stage. |
| Mapping ring_osc2x13.dstage[7].id using delay_stage. |
| Mapping ring_osc2x13.dstage[8].id using delay_stage. |
| Mapping ring_osc2x13.dstage[9].id using delay_stage. |
| Mapping ring_osc2x13.dstage[10].id using delay_stage. |
| Mapping ring_osc2x13.dstage[11].id using delay_stage. |
| Mapping ring_osc2x13.iss using start_stage. |
| No more expansions possible. |
| Deleting now unused module delay_stage. |
| Deleting now unused module start_stage. |
| |
| 8. Executing SETUNDEF pass (replace undef values with defined constants). |
| Removed 0 unused cells and 28 unused wires. |
| |
| 9. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 10. Executing HILOMAP pass (mapping to constant drivers). |
| |
| 11. Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells). |
| Mapping port ring_osc2x13.clockp using scs8hd_buf_1. |
| Don't map input port ring_osc2x13.reset: Missing option -inpad. |
| Don't map input port ring_osc2x13.trim: Missing option -inpad. |
| |
| 12. Executing OPT pass (performing simple optimizations). |
| |
| 12.1. Executing OPT_EXPR pass (perform const folding). |
| |
| 12.2. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\ring_osc2x13'. |
| Removed a total of 0 cells. |
| |
| 12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). |
| Running muxtree optimizer on module \ring_osc2x13.. |
| Creating internal representation of mux trees. |
| No muxes found in this module. |
| Removed 0 multiplexer ports. |
| |
| 12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). |
| Optimizing cells in module \ring_osc2x13. |
| Performed a total of 0 changes. |
| |
| 12.5. Executing OPT_MERGE pass (detect identical cells). |
| Finding identical cells in module `\ring_osc2x13'. |
| Removed a total of 0 cells. |
| |
| 12.6. Executing OPT_RMDFF pass (remove dff with constant values). |
| |
| 12.7. Executing OPT_CLEAN pass (remove unused cells and wires). |
| Finding unused cells or wires in module \ring_osc2x13.. |
| Removed 0 unused cells and 28 unused wires. |
| |
| 12.8. Executing OPT_EXPR pass (perform const folding). |
| |
| 12.9. Finished OPT passes. (There is nothing left to do.) |
| |
| 13. Executing Verilog backend. |
| Dumping module `\ring_osc2x13'. |
| |
| 14. Printing statistics. |
| |
| === ring_osc2x13 === |
| |
| Number of wires: 71 |
| Number of wire bits: 99 |
| Number of public wires: 71 |
| Number of public wire bits: 99 |
| Number of memories: 0 |
| Number of memory bits: 0 |
| Number of processes: 0 |
| Number of cells: 99 |
| scs8hd_buf_1 2 |
| scs8hd_clkbuf_1 13 |
| scs8hd_clkbuf_2 12 |
| scs8hd_clkinv_1 13 |
| scs8hd_clkinv_2 2 |
| scs8hd_clkinv_8 2 |
| scs8hd_conb_1 1 |
| scs8hd_einvn_4 13 |
| scs8hd_einvn_8 13 |
| scs8hd_einvp_1 1 |
| scs8hd_einvp_2 26 |
| scs8hd_or2_2 1 |
| |
| Warnings: 5 unique messages, 9 total |
| End of script. Logfile hash: 05e0acd086 |
| CPU: user 2.71s system 0.03s, MEM: 66.19 MB total, 38.04 MB resident |
| Yosys 0.8+17 (git sha1 11c8a9eb, gcc 4.7.4 -fPIC -Os) |
| Time spent: 53% 1x share (1 sec), 15% 2x read_liberty (0 sec), ... |
| Running getpowerground to determine power and ground net names. |
| getpowerground.tcl /ef/tech/SW/EFS8A/libs.ref/lef/scs8hd/scs8hd.lef |
| Running vlogFanout |
| vlogFanout -l 200 -c 20 -I ring_osc2x13_nofanout -s nullstring -p /ef/tech/SW/EFS8A/libs.ref/lib/scs8hd/scs8hd_ff_1.95v_-40C.lib -b scs8hd_buf_1,scs8hd_clkbuf_1 -i A,A -o X,X ring_osc2x13_mapped.v ring_osc2x13_sized.v |
| |
| vlogFanout for qflow 1.4.73 |
| Parsing library "scs8hd_ff_1.95v_-40C" |
| End of library at line 171209 |
| Lib Read: Processed 171210 lines. |
| Top internal fanout is 3 (load 440693) from node \dstage[1].id.ts , |
| driven by scs8hd_clkbuf_2 with strength 73.0132 (fF driven at latency 200) |
| Top fanout load-to-strength ratio is 0.586158 (latency = 117.232 ps) |
| Top input node fanout is 2 (load 13.801) from node reset. |
| 0 gates exceed specified minimum load. |
| 0 buffers were added. |
| 2 gates were changed. |
| |
| Gate counts by drive strength: |
| |
| "1" gates In: 31 Out: 29 -2 |
| "2" gates In: 41 Out: 43 +2 |
| "4" gates In: 13 Out: 13 +0 |
| "8" gates In: 15 Out: 15 +0 |
| |
| 0 gates exceed specified minimum load. |
| 0 buffers were added. |
| 0 gates were changed. |
| |
| Gate counts by drive strength: |
| |
| "1" gates In: 31 Out: 29 -2 |
| "2" gates In: 41 Out: 43 +2 |
| "4" gates In: 13 Out: 13 +0 |
| "8" gates In: 15 Out: 15 +0 |
| |
| Number of gates changed: 0 |
| Running vlog2Verilog for antenna cell mapping. |
| vlog2Verilog -c -p -v vpwr,vpb -g vgnd,vnb -l /ef/tech/SW/EFS8A/libs.ref/lef/scs8hd/scs8hd.lef -a scs8hd_diode_ |
| -o ring_osc2x13.v ring_osc2x13_sized.v |
| |
| Generating RTL verilog and SPICE netlist file in directory |
| /home/tim/gits/openstriVe/qflow/ring_osc2x13/synthesis |
| Files: |
| Verilog: /home/tim/gits/openstriVe/qflow/ring_osc2x13/synthesis/ring_osc2x13.rtl.v |
| Verilog: /home/tim/gits/openstriVe/qflow/ring_osc2x13/synthesis/ring_osc2x13.rtlnopwr.v |
| Verilog: /home/tim/gits/openstriVe/qflow/ring_osc2x13/synthesis/ring_osc2x13.rtlbb.v |
| Spice: /home/tim/gits/openstriVe/qflow/ring_osc2x13/synthesis/ring_osc2x13.spc |
| |
| Running vlog2Verilog. |
| vlog2Verilog -c -v vpwr,vpb -g vgnd,vnb -l /ef/tech/SW/EFS8A/libs.ref/lef/scs8hd/scs8hd.lef |
| -o ring_osc2x13.rtl.v |
| ring_osc2x13.v |
| vlog2Verilog -c -p -v vpwr,vpb -g vgnd,vnb -l /ef/tech/SW/EFS8A/libs.ref/lef/scs8hd/scs8hd.lef |
| -o ring_osc2x13.rtlnopwr.v |
| ring_osc2x13.v |
| /ef/efabless/share/qflow/bin/vlog2Verilog -c -p -b -n -v vpwr,vpb -g vgnd,vnb -l /ef/tech/SW/EFS8A/libs.ref/lef/scs8hd/scs8hd.lef |
| -o ring_osc2x13.rtlbb.v |
| Running vlog2Spice. |
| vlog2Spice -i -l /ef/tech/SW/EFS8A/libs.ref/spi/scs8hd/scs8hd.spi -o ring_osc2x13.spc ring_osc2x13.rtl.v |
| Running spi2xspice.py |
| spi2xspice.py "/ef/tech/SW/EFS8A/libs.ref/lib/scs8hd/scs8hd_ff_1.95v_-40C.lib" -io_time=500p -time=50p -idelay=5p -odelay=50p -cload=250f ring_osc2x13.spc ring_osc2x13.xspice |
| |
| Synthesis script ended on Thu Feb 27 08:46:24 PST 2020 |
